Posted on May 17, 2011 at 13:14Quote:
On 09-06-2009 at 21:18, Anonymous wrote:
So, in first program:
R0 contain GPIOA high address ODR 0x4001080D
R1 contain address of memory buffer (in RAM), where from will read data
in second program:
R0 contain GPIOA low address IDR 0x40010808
R2 contain address of memory, where will write data of input port
I believe that R2 at the end is R1, right ? and was a typo, In that case this is easy not so difficult to explain , I have replaced R1 and R0 by their meaning :
Quote:
LDRB R2, [Internal RAM]
STRB R2, [GPIO DR]
LDRB R2, [Internal RAM]
STRB R2, [GPIO DR]
....etc.
Above code need 8 cycles, but other program:
LDRB R2, [GPIO DR]
STRB R2, [Internal RAM]
LDRB R2, [GPIO DR]
STRB R2, [Internal RAM]
.... etc.
need to execute 14 cycles!!! Why?
GPIO DR are located in the ''High speed APB'' bus after the AHBtoAPB Bridge
whereas The internal RAM is located at AHB Bus, In fact inside the AHBtoAPB bridge there is a ''write Buffer'' that buffers the writes to the APB locations. That this why in the first case the timing is minimum, However in the second case, when you load from ''APB'' using the LDRB, which is a blocking instruction, the high speed APB needs 1 additional cycle compared to RAM if the APB/AHB prescaler is equal to 1.
Hope this explains to you results.
Cheers,
STOne-32.
