Posted on May 17, 2011 at 13:20It's like this because the sampling must take a certain number of clock cycles, where that number is 12.5 + whatever sampling time you specify. The fast sampling speed available is 1.5 cycles, so you can assume that the values given are at 14 cycles per sample.
PCLK2 can be divided by 1, 2, etc, and the ADC clock can be divided from there by 2, 4, 6, or 8. So your combined divider off of the sysclock will be 1, 2, 4, or 6 - nothing higher is relevant for the clock speeds you've selected.
So at 72MHz the lowest effective divider you can use is 6, giving 12MHz. Since a conversion takes 14 cycles, this means the effective sampling rate is 0.857MHz, or 1.17 uS periods as you mentioned. You can't use a divider of 4, because that would exceed the hardware limitations of the ADC - it needs to have at least 1 uS of sampling time. At 56MHz, however, you can use the 4 divider and get effectively that.
I hope that clears things up.
