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FSMC interfacing with NAND flash

info145
Associate
Posted on November 15, 2009 at 16:02

FSMC interfacing with NAND flash

3 REPLIES 3
info145
Associate
Posted on May 17, 2011 at 13:20

When a ''Read ID'' of the Samsung K9F1208U0C is done in STM32F103VE,

the expected waveform is:

CLE ___----_____________________

ALE ___________----_____________

However, the observed waveform is:

CLE ___----___-____--___________

ALE ___________----_____________

K9F1208U0C does not respond to the request due to the CLE issues.

Other observations:

When only CLE operations are done in a loop, the observed waveforms are clean.

When only ALE operations are done in a loop, the observed waveforms are clean.

When a CLE operation is followed by an ALE operation, the waveform is not clean.

There is a work-around that seems to work, but it has not been tested for other operations yet.

The Standard Peripheral Library sample code programs the GPIOD, Pin 11 (CLE) as GPIO_Mode_AF_PP and the FSMC_NAND_ReadID function uses the following sequence:

*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = 0x90;

*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;

Instead, if the pin is configured as GPIO_Mode_Out_PP, and the sequence is modified as follows:

GPIO_SetBits(GPIOD, GPIO_Pin_11);

*(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = 0x90;

GPIO_ResetBits(GPIOD, GPIO_Pin_11);

*(__IO uint8_t *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;

the waveforms look like the expected waveforms and K9F1208U0C responds correctly.

Essentially, we are controlling the waveform from software, and the ReadID operation works correctly. This suggests that it is not a board related issue, but some issue related to FSMC.

Is there any FSMC mis-configuration that could cause this issue ? Has anyone observed such an issue ?

- Yantra

janis2
Associate II
Posted on May 17, 2011 at 13:20

By working more I managed to get my flash to work. Initial problem was wrong pin setup. When I fixed that my flash started to reply on the Device ID request.

CLE signal from STM32 still looks a little weird but seems that it does not affect flash operation. Software workaround as suggested by info93 didn't work for me because when I set CLE to Out_PP no data is latched on the data pins by command *(__IO uint8_t *)(Bank_NAND_ADDR | CMD_AREA) = 0x90;

Anyway, for correct pin setup I need new pcb and then I will able to test more than just Device ID flash request.

--

Janis

janis2
Associate II
Posted on May 17, 2011 at 13:20

Hello!

I am encountering the same exact problem. Has there been any solution? Software workaround would not be preferred method.

Thank you in advance,

Regards,

Janis