Stepper motor, timer phase control

[picguy2]

Posted on August 07, 2014 at 23:26

I am setting up stepper motor control on an STM32F4xxx using Full Step Drive as in http://en.wikipedia.org/wiki/File:Drive.png

Both timers are setup as up counters with PWM output. Timer 2 controls phases A & C. Timer 5 controls phases B & D.  Example with fixed frequency:TIMER 2CNT = 4000CCR1 = 2000 (CNT/2)CCR2 = 2000 (with complement output)CCR3 = 1000 (CNT/4)TIMER 5CNT = 4000CCR3 = 2000CCR4 = 2000 (with complement output)GPIO setup to output on PA0..PA3I need something like timer 2 CCR3 rising edge to reset timer 5.  Specifically to reset timer 5 counter to zero and to load CNT, CCR3 and CCR4 from their shadow registers.The stepper motor must have a variable speed.  For speed changes timer 2 interrupts on counter reload.  In the ISR its CNT, CCR1, CCR2 and CCR3 are changed unbuffered.  (No change is more than 2%.)  At the same time timer 5�s CNT, CCR3 and CCR4 registers are changed to go into effect when timer 2 triggers reset via ITR0 (TRGO from CCR3).At least that�s how it�s supposed to work.However, docs are fuzzy about the various settings to make all this work. I likely have most of it:TIMER 2 (master)CR1 = 1 (simple on, unbuffered, up count etc)CR2  MMS = 110b (OC3REF signal is used as trigger output -- TRGO)SMCR  top 8 bits all zero  TS = 000b (is this important for ITR0?)  SMS = 000b (Does this means timer 2 is the master?)CCMR2  OC3CE = 0   OC3M = 110b (standard positive PWM output)  OC3PE = 0 (new CCR3 takes effect immediately - also OC1PE & OC2PE)  OC3FE = 0 (is this bit irreverent here?)  CC3S = 00b (output mode)TIMER 5 (slave)CR1 = 0x85 (on, buffered, )  APPE = 1 (buffered ARR)  URS = 1 (What does this do? Anything?)  CEN = 1 enable counterCR2  MMS = 000b (what�s the value most likely to be ignored?)SMCR  top 8 bits all zero  MSM = 0  TS = 000b (use internal trigger ITR0)  SMS = 100b (trigger forces slave to act like counter hit max??)CCMR2  MSM = 0  (x=3 and 4)  OCxCE = 0 (whatever does this do?)  OC3M = 110b  OC4M = 111b  OCxPE = 0 (is this correct for buffered?)  OCxFE = 0 (is this correct for buffered?)  CCxS = 00b (output mode)Yet when the millisecond timer takes my OS out of WFI both CNT registers are equal.  What don�t I understand? #stepper-motor #timer-phase

[Tesla DeLorean]

Posted on August 08, 2014 at 01:34

For phase relative control from a single timer consider using toggle mode, and advancing\retarding CCRx points to control edge/phase placement.

[picguy2]

Posted on August 08, 2014 at 02:48

Good thought.  Thanks.  Toggle phases A & C using CCR1=CCR2=1.  Toggle phases B & D using CCR3=CCR4=(CNT/2)+1.  And that only uses one timer!

  But can I set starting outputs on PA0..3 by setting GPIOA_BSRR to 0x000A0005?  Or is the start point for toggles contained within the timer?  Setting BSRR is a piece of cake.  Finding something hidden within the timer could be a problem..Assuming BSRR works (fingers crossed) reverse (after stopping the timer) is likely a simple BSRR=0x00060009.  Will try sometime next week using a logic analyzer.