Is it possible to change SPI datasize when ever by writing a new setting to the SPI_CR1.DFF?

[sima2]

Posted on May 09, 2012 at 11:13

Is it possible to change SPI datasize when ever by writing a new setting to the SPI_CR1.DFF?

I need to communicate with two devices on the same SPI bus. On uses 8 bits and the other 16 bits.

[jado]

Posted on May 09, 2012 at 15:06

Yes, it's possible.

Look at this:     SPI1->CR1 &= B16(11111111,10111111); // disable SPI1     SPI1->CR1 |= B16(00001000,00000000); //DFF = 1 -> 16 bit SPI mode     SPI1->CR1 |= B16(00000000,01000000); // enable SPI1and this:     SPI1->CR1 &= B16(11111111,10111111); // disable SPI1     SPI1->CR1 &= B16(11110111,11111111); //DFF = 0 -> 8 bit SPI mode     SPI1->CR1 |= B16(00000000,01000000); // enable SPI1You can use hex values instead of binary, of course...

[sima2]

Posted on May 10, 2012 at 11:02

Thank you. I tested it, but I didn't have to disable the SPI while changing the bit length.

[emalund]

Posted on May 14, 2012 at 16:19

why even bother switching length?

16 bits = 2*8 bits, send 2 bytes. In SPI there is no ''byte separation'' tranmitting twice fron an 8bit device will be see cvorrectly by a 16-but device. Erik  

[jado]

Posted on May 15, 2012 at 18:18

When you use interrupts, it's better to load data to transmit register once for 2 bytes than every byte.  So interrupt occurs twice times slower. Then you have more time to do other things 🙂

Other processors have even more datasizes - PIC32 has up to 4 bytes at once, some others may have fifo's, etc....--Jado 

[Tesla DeLorean]

Posted on May 15, 2012 at 20:19

When you use interrupts, it's better to load data to transmit register once for 2 bytes than every byte.  So interrupt occurs twice times slower. Then you have more time to do other things 🙂

Other processors have even more datasizes - PIC32 has up to 4 bytes at once, some others may have fifo's, etc....

Yes, the STM32 is rather inflexible with SPI word bit lengths. DMA however is used in place of FIFOs, and ideally suited to transmission of data blocks. If you're interrupting every byte/word you could probably free that time up for useful work. I'd certainly like to have seen receive FIFOs on the USARTs Then again if you wanted the perfect chip you'd be doing SOC not COTS.