Posted on November 26, 2011 at 11:13Hi,
There is a small conceptual issue I wish to report in the STM32F2/F4/L1 headers.
Currently the GPIO BSRR register is declared as two separated 16bits registers BSRRL and BSRRH which defeats its purpose of making atomic masked writes possible, that requires a single 32bits access.
I recommend redefining it as an union allowing both access modes:
volatile union {
uint32_t W;
struct {
uint16_t set;
uint16_t clear;
} H;
} BSRR;
This would make possible both simple and masked accesses.
Giovanni
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