Posted on May 17, 2011 at 13:471) The unit is rated/tested for 36 MHz operation, it might run higher, at some point the PLL/VCO could malfunction, or timing requirements (setup, hold, propagation) are violated. The system doesn't care what the frequency is. If you exceed the speed of the underlying silicon the chip will malfunction, but is unlikely to be damaged provided power/heat limits are not exceeded.
2)
SYSCLK = System clock (CPU, NVIC)
HCLK - Hardware bus clock AHB (CPU view of external units)
PCLK1 = Peripheral bus clock APB1 (Lower speed peripherals)
PCLK2 = Peripheral bus clock APB2 (Higher speed peripherals)
MCO = Main Clock Output (External clock output from device)
http://www.st.com/stonline/products/literature/ds/13586.pdf See pg 18 for a diagram
3) USART1 is driven by APB2 (PCLK2), max baud at 36MHZ 2.250 Mbaud, the other USART2..5 are driven by APB1 (PCLK1), max baud at 36MHz 2.250 Mbaud, at 24MHz 1.5 Mbaud (ie PCLK1 / 16). The accuracy (%error) of your baud rate will be dependent on your source clock.
4) Relates to how strongly the pins are driven to control the slew rate. The rise/fall times are tighter at higher speeds, more drive is required to overcome external trace capacitance to achieve the desired rate. If you don't need the higher speed, use a lower one to reduce power consumption, and reduce overshoot.
