cancel
Showing results for 
Search instead for 
Did you mean: 

I2S Transmit data on clocks falling edge, rather than rising edge?

Paul UHS
Associate II
Posted on March 03, 2014 at 00:52

Hi All,

I am implementing an application of using I2S to transmit audio to a SLIC. My I2S setup is the following.

/* I2S peripheral configuration */

SPI_I2S_DeInit(SPI_SLIC_AUDIO);

I2S_InitStructure.I2S_AudioFreq  = I2S_AudioFreq_8k;

I2S_InitStructure.I2S_Standard   = I2S_Standard_MSB;

I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16bextended;

I2S_InitStructure.I2S_CPOL       = I2S_CPOL_Low;

I2S_InitStructure.I2S_Mode       = I2S_Mode_MasterTx;

I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Enable;

/* Initialize the I2S peripheral with the structure above */

I2S_Init(SPI2, &I2S_InitStructure);

/* Configure the I2Sx_ext (the second instance) in Slave Receiver Mode */

I2S_FullDuplexConfig(I2S2ext, &I2S_InitStructure);

/* Enable the I2Sx peripheral */

I2S_Cmd(SPI2, ENABLE);

/* Enable the I2Sx_ext peripheral for Full Duplex mode */

I2S_Cmd(I2S2ext, ENABLE);

I then am running a continuous DMA in circular buffer mode to continuously transmit the PCLK.

This all works fine, clocks come out, data comes out, data is received etc.

Perfect, apart from 1 problem. The clock/data transition polarity is wrong. I need data to be transmitted on the falling edge then when my SLIC samples on the clocks rising edge, everything will have stabilised.

I orginally thought that ''I2S_InitStructure.I2S_CPOL = I2S_CPOL_High;'' would solve this, but it seems it only sets the idle position of the clock during periods of no data being sent, not when data is transmitted. It always transmits on the rising edge.

I have captured this behaviour on the scope and can upload if need be, but its not very interesting. Rising edge data transition. I have verified the that the I2S register is changing values for the two different settings of I2S_CPOL_Low & I2S_CPOL_High.

Does anyone have any ideas, other than placing an inline clock inverter? (not sure if that will work either though due to receive, and internal I2Sext setup, I hope I can change the PCM slot to allow for this possibility). Any ideas would be greatly appreciated.

Regards Paul
1 REPLY 1
Paul UHS
Associate II
Posted on March 03, 2014 at 08:42

Managed to get an acceptable solution, using the PCM I2S interface, and instead just using a 256kHz PCLK output, rather than 512kHz output.