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I2S MCLK runs too fast!

jensen006
Associate II
Posted on June 07, 2010 at 16:01

I2S MCLK runs too fast!

#programming-i2s
14 REPLIES 14
chikos332
Associate II
Posted on May 17, 2011 at 13:54

Hi Thomas,

First, it depends on which device you are using: (connectivity line (STM32F105/7) or high-density line (STM32F103/5)).

Second, are you sure that you have Fs = 48 KHz ? could you please tell us the PLL dividers/multipliers and the I2S dividers (I2SDIV and I2SODD) you are using ?

for example: for high density line, when system is running on 72MHz, you should have I2SDIV = 3 and I2SODD = 0...

It would be nice if you share the piece of code where you configure the I2S ...

Cheers.

jensen006
Associate II
Posted on May 17, 2011 at 13:54

The original post was too long to process during our migration. Please click on the provided URL to read the original post. https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006I6Z7&d=%2Fa%2F0X0000000bqo%2FdPkvsfbc2P6ldg18zquNHYHkaqi54LZ2nrKbggXmVjQ&asPdf=false
chikos332
Associate II
Posted on May 17, 2011 at 13:54

Hi Thomas,

That's really strange! I used your entire code and load it in an STM32F103. I had 12MHz on PC6 and 3MHz on PB13 which are the correct values (I also tried other frequencies and always have correct values)...

There should be something wrong somewhere else (startup file, hardware, interrupt ...).

If you have the possibility to ''see'' the RCC registers and the SPI registers it would help debug the issue (you should see RCC_CFGR=0x30353803 and RCC_CR=0x001D240A register as well as the SPI2_I2SPR=0x0203 and SPI2_I2S_CFGR=0x0E01.... these are the values I have when I run your software) .

If you have the write values... then something should be wrong in the hardware ... I see that you configure PC6 as LED also, are you using this pin for other purposes ? are you using ST evaluation board (STM32F10E-EVAL) or one other board? Did you do some modifications on the board ?

I hope this help you find the issue source.

Cheers.

Posted on May 17, 2011 at 13:54

Check the frequency of the external oscillator.

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jensen006
Associate II
Posted on May 17, 2011 at 13:54

I'm running this eval board:

http://www.st.com/stonline/products/literature/um/15867.pdf

which has an on-board 16Mhz crystal so could that be the case that I get twice the MLCK frequency using the clock-divider settings presented?

If I change:

        RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);

to:

        RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_3);

I get the right clock (12mhz) but doesn't that affect the core frequency of the ARM core too (which I don't want as I need the full 72mhz)?

Can I somehow probe the clock signal the goes to the ARM core?

Hope you can reserve a little more time with this problem - I have the feeling we are pretty close solving this!

Thanks

Thomas

chikos332
Associate II
Posted on May 17, 2011 at 13:54

Hi,

''I have the feeling we are pretty close solving this!''

Yes indeed 🙂

I think the issue is this define:

''HSE_VALUE'' or ''HSE_Value'' (depends on the version of firmware library you are using) in the file stm32f10x.h in folder CMSIS/CM3/DeviceSupport/ST/STM32F10x (if you have the latest version).

You should set this define to the right value of your external crystal because the default value is 25MHz while you have 16MHz ...

Just look for this define and modify it and everything will be OK 🙂

Thanks Clive for the hint 🙂

Good luck.
Posted on May 17, 2011 at 13:54

Divide the input to the PLL by 2

RCC_PLLConfig(RCC_PLLSource_HSE_Div2, RCC_PLLMul_9);

PLLout =  (16 MHz / 2) * 9 = 72 MHz

Wow the forum is putting answers out of order. Great job Microsoft.
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jensen006
Associate II
Posted on May 17, 2011 at 13:54

Damn it  🙂

I still don't reach the 12.8Mhz ..I misread the scope output.

The SYSCLK is 72MHZ is and this goes directly to the I2S interface so the clock decimation has to be done there. I haven't succeeded making this work.

Clive, by doing what you suggest the SYSCLK changes to 36MHZ which I can't live with. But it does give the right I2S clock

Any suggestions?

Best Regards

Thomas

Yeah the posting order is wrong here

Posted on May 17, 2011 at 13:54

Are you sure you are using HSE? and that it is 16 MHz

RCC_PLLSource_HSE_Div2 and a multiplier of 9 should give a 72 MHz SYSCLK for a 16 MHz source. If it is not something is very wrong.

My boards use 8MHz HSE/HSI, so can't check it myself.

If you use RCC_PLLSource_HSI_Div2 you will get 36 MHz

Damn this forum is screwy, why exactly did ST migrate from the old one that worked so nicely?
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