Posted on April 04, 2013 at 22:17My company uses a nifty tool called ScanExpress that takes your netlist, parts list, and BSDL files for the JTAG chain and creates an automated test using the Boundary scan to see if all the connections are correct. We've used it successfully for some FPGA/DSP/Memory type boards.
So, I have a design with two STM32F103 ICs in a chain. They are the only two JTAG devices on the board. I had to create fake IC's in the chain since each STM32 device has two JTAG devices inside and two BSDL files. The chain looks like this:
TDI -> STM32&sharp1 M3&sharp1 -> STM32&sharp2 M3&sharp2 -> TDO
When I run the JTAG test, it fails one of the setup tests: (results below)
Expanded IR Capture Test: Passed
IDCODE Test: Failed
TDI
U2 (STM32F1_High_density_LQFP64)
ACT: 11111
EXP: XXX01
U22 (CortexM3)
ACT: 0001
EXP: 0001
U3 (STM32F1_High_density_LQFP64)
ACT: 11111
EXP: XXX01
U33 (CortexM3)
ACT: 0001
EXP: 0001
TDOI opened the BSDL file for the STM32F2 and changed the ID line:
FROM:
attribute INSTRUCTION_CAPTURE of STM32F1_High_density_LQFP64: entity is ''XXX01''TO: attribute
INSTRUCTION_CAPTURE of STM32F1_High_density_LQFP64: entity is ''XXXXX'';The 'X's I assume are don't cares. It all works now and can do the bound-scan port magic.
My question is, why did it fail that test in the first place?
#stm32-bsdl-jtag-boundary
