Posted on May 17, 2011 at 14:12This reply does not address ST’s interface code.
In general terms: events may or may not generate interrupts. STM32 processors are far from unique in that
events set flags that software can see and reset. Interrupts may be enabled on these events. When an event causes an interrupt the responding ISR generally has to reset the event by some action.
Example RS-232 receiver has data, data ready flag set, ISR invoked (interrupt was already enabled), ISR code reads data register, hardware resets data ready flag. When done the ISR exits.
Software can generate events. For some devices, the equivalent of setting the data ready bit constitutes an event which may cause an interrupt.. The SVC instruction (think of it as an event) causes an interrupt. An ISR (or any software with access to the flags) may set the interrupt pending flag on any interrupt.
