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Clock configuration for stm32l432

Posted on April 07, 2018 at 03:44

I am working on a project with stm32l432kb. It uses 8 MHz external clock in order to achieve 80 MHz system clock. I've configured clock with the Cube. The diagram shows system clock at 80 MHz, nevertheless the real clock seems to be about 16 MHz. Reading clock with  HAL_RCC_GetHCLKFreq() gives value of 15875000. I've verified that the defined HSE_VALUE is 8 MHz. Here is the Cube generated code for clock configuration:

void SystemClock_Config(void)

{

RCC_OscInitTypeDef RCC_OscInitStruct;

RCC_ClkInitTypeDef RCC_ClkInitStruct;

RCC_PeriphCLKInitTypeDef PeriphClkInit;

/**Initializes the CPU, AHB and APB busses clocks

*/

RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;

RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;

RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;

RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;

RCC_OscInitStruct.PLL.PLLN = 40;

RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;

RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;

RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV4;

if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)

{

_Error_Handler(__FILE__, __LINE__);

}

/**Initializes the CPU, AHB and APB busses clocks

*/

RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK

|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;

RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;

RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;

RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;

RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;

if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)

{

_Error_Handler(__FILE__, __LINE__);

}

PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;

PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;

if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)

{

_Error_Handler(__FILE__, __LINE__);

}

/**Configure the main internal regulator output voltage

*/

if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)

{

_Error_Handler(__FILE__, __LINE__);

}

/**Configure the Systick interrupt time

*/

HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);

/**Configure the Systick

*/

HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);

/* SysTick_IRQn interrupt configuration */

HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);

}

What can be wrong with configuration?

Thank you

1 ACCEPTED SOLUTION

Accepted Solutions
Szymon PANECKI
Senior III
Posted on April 07, 2018 at 10:02

Hello,

In one of non up to date SM32CubeMX revisions there was an issue with correct code generation for STM32L4 clock configuration. The issue was that PLLM parameter was set to different value than indicated by STM32CubeMX and as a result system clock frequency was not correct (lower than expected). For example STM32CubeMX was indicating PLLM  = 1, while the generated code was using something else.

0690X0000060ASEQA2.png

Here in your code I don't see PLLM parameter, so maybe this could be a root cause. Could you please try to add PLLM parameter between those two lines of code?:

RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;

RCC_OscInitStruct.PLL.PLLN = 40;

I guess that in your case PLLM is equal to 1, so it would look like this:

RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;

RCC_OscInitStruct.PLL.PLLM = 1;

RCC_OscInitStruct.PLL.PLLN = 40;

Could you please try this solution and let us know if it helps?

Anyway please make sure that you use the latest revisions of STM32CubeMX and STM32L4Cube package.

Regards

Szymon

View solution in original post

15 REPLIES 15
Posted on April 07, 2018 at 04:04

Is this an external source, or a crystal?

Can you try selecting the various internal clocks and outputting via PA8 (MCO) pin?

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Posted on April 07, 2018 at 05:39

It's an external clock. I will try to do what you recommend. Unfortunately, PA8 is an input from external source, But I will try to come up with the solution.  

Jan Waclawek
Senior II
Posted on April 07, 2018 at 09:43

Read out and check/post the relevant RCC registers.

Did you fill in all RCC_OscInitStruct fields?

JW

Szymon PANECKI
Senior III
Posted on April 07, 2018 at 10:02

Hello,

In one of non up to date SM32CubeMX revisions there was an issue with correct code generation for STM32L4 clock configuration. The issue was that PLLM parameter was set to different value than indicated by STM32CubeMX and as a result system clock frequency was not correct (lower than expected). For example STM32CubeMX was indicating PLLM  = 1, while the generated code was using something else.

0690X0000060ASEQA2.png

Here in your code I don't see PLLM parameter, so maybe this could be a root cause. Could you please try to add PLLM parameter between those two lines of code?:

RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;

RCC_OscInitStruct.PLL.PLLN = 40;

I guess that in your case PLLM is equal to 1, so it would look like this:

RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;

RCC_OscInitStruct.PLL.PLLM = 1;

RCC_OscInitStruct.PLL.PLLN = 40;

Could you please try this solution and let us know if it helps?

Anyway please make sure that you use the latest revisions of STM32CubeMX and STM32L4Cube package.

Regards

Szymon

Posted on April 07, 2018 at 16:01

Yes, PLLM assignment was missing, and I haven't paid attention.

Inserting 

RCC_OscInitStruct.PLL.PLLM = 1;

solved the problem.

My fault - I needed to verify the registers

:(

Thanks a lot to everyone for taking time to help me with this issue.

Gennady 

Posted on April 07, 2018 at 16:09

As it was also mentioned in another post (Szymon Panecki), the PLLM assignment was missing. Assigning it to 1 solved the problem. 

Thanks a lot,

Gennady

Posted on April 07, 2018 at 16:15

BTW, both 

STM32CubeMX and STM32L4Cube package I used are up to date. So it seems that the issue with clock configuration for

STM32L4 

still exists.

Gennady 

 
Posted on April 12, 2018 at 18:41

Hi Gennady, 

I am also trying achieve same same system clock frequency as what you are doing. 

Shouldn't your PLL_N be set to 10 for VCO clock frequency of 80MHz with PLL clock input as 8MHz and PLL_M=1?

regards

R

Posted on April 12, 2018 at 19:27

I'd presume in the OPs case that the PLLM selection was something other than 1, but one would need to review the DS/RM to confirm the specific PLL comparison frequency range for the L4 which I don't think is the 1-2 MHz of the F4 series.

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