DAC output buffer - DC offset

CanisSomnolentus · ‎2012-07-04

Posted on July 04, 2012 at 21:33

Hallo,

I have not found, in the stm32f100x reference manual or data sheet, any mentioning of a DC offset on the DAC.

But if use DAC_OutputBuffer_Enable, I get ~ 60 mV on the pins (nothing connected but a scope) when constantly writing zeroes to the DAC.

Is that normal behavior for an stm32, or is it some qirk on the discovery board?

Or perhaps, my stm32 is on the far end of tolerance or something ...

Regards

raptorhal2 · ‎2012-07-04

Posted on July 05, 2012 at 00:56

60 mv does seem high. I presume you have set the pin to AN mode, and are using a common ground for the Discovery and scope. To spot ground problems, send 0xFFF to the DAC and see if the result is VREF + 60 mv.

Cheers, Hal

frankmeyer9 · ‎2012-07-04

Posted on July 05, 2012 at 08:54

It's in the datasheet, in the electrical characteristics of the DAC. I have checked it for the F0, assuming the peripheral unit is similiar for other devices.

There is a DAC_out(min) and DAC_out(max) given with buffer, and a DAC_out(min) and DAC_out(max) without buffer. According to the F0 datasheet, you can have an zero offset of up to 0.2V with buffer on, and reach only (Vdd-0.2V).

If this is a problem, try an external buffer amplifier.

CanisSomnolentus · ‎2012-07-05

Posted on July 05, 2012 at 15:09

ah, thanks, those were good search words, I must have overlooked this.

A problem, well, for one channel it is, for one not. Since IIRC both channels are configurable independently, it shouldn't be a problem.

Now that section also states:

''When the buffer is OFF, the

Minimum resistive load between

DAC_OUT and VSS to have a

1% accuracy is 1.5 MΩ''

Does that mean, at least 1.5MΩ, or greater (that'd be weird), or ''minimum load'', as in ''smaller resistance = greater load''. i.e. should be <= 1.5MΩ ?

frankmeyer9 · ‎2012-07-05

Posted on July 05, 2012 at 15:45

ah, thanks, those were good search words, I must have overlooked this.

If memory serves me well, there was also a cryptic note in the reference manual about the (slightly) reduced output swing with activated buffer amplifier. By the way, 60mV is not bad for an rail-to-rail opamp, the stated 200mV are normal, I think.

Does that mean, at least 1.5MΩ, or greater (that'd be weird), or ''minimum load'', as in ''smaller resistance = greater load''. i.e. should be <= 1.5MΩ ?

It is to understand as current load. 1.5MOhm cause a very small current, compared to the maximum stated load of 15kOhm. With that small resistive loads, the (parasitic) capacitive load component is going to dominate the response, creating a substantial phase shift and decreased accuracy. But I agree with you, the wording is somehow weird.

I don't know your application, but without internal buffer amplifier activated, you will probably need an external amplifier. Even with an external rail-to-rail opamp, you will hardly get closer to 0.0V if you don't have a negative supply voltage (i.e. V(-) of the opamp is below GND level of the STM32).

CanisSomnolentus · ‎2012-07-05

Posted on July 05, 2012 at 18:28

Ah, that makes sense, thanks for clearing up.

Yeah I just recently built a +/- 5V power supply which I power my not quite rail-to-rail op-amps with 🙂

raptorhal2 · ‎2012-07-05

Posted on July 05, 2012 at 22:22

Ro of 15K with the buffer OFF is the DAC internal output impedance. The 1.5M applies to the external load. 15K/1.5M = 1%. So you need at least a 1.5M load to get 1% accuracy. As fm states, this is best achieved by feeding to the high input impedance of a buffer amplifier.

Cheers, Hal