A few questions on the STM32L...

[shotaro]

Posted on April 09, 2012 at 18:46

1. Is there a proper way to go into low-power sleep? When I try to step through in the debugger (or at least, let the program run and then pause it), the LPSDSR flag never gets set. And when I let the program run without a debugger, an ammeter I've hooked up doesn't seem to show any difference.
2. I'm trying to run a timer through an external clock. I got as far as getting it to run, but it always stops for no real reason. After initializing the timer and setting the CEN flag, I step through another line of code, turn on my external clock, and then step over the next line of code. I see the counter changed, but when I step again, CEN is 0. Any idea what's going on? This does not happen if I use the internal clock.

Thanks!

EDIT: Never mind about #2. I realized after posting that I had a timer interrupt that checks for something and it disables the timer if that condition is met.

[shotaro]

Posted on April 09, 2012 at 20:22

Hate to post in my own thread but...

Even though I have an external oscillator (provided by a function generator) running the timer through TI2, I've noticed some anomalies while messing around with this setup.

• When I tell the timer to output at half the frequency of the oscillator (at 1 MHz), there's a phase shift of about half the frequency with respect to the oscillator. My colleague suspects there's some kind of propagation delay.
• When I increase the external oscillator frequency, the timer increases its frequency until about 8MHz. At that point, the timer's output decreases in frequency. At 15MHz (the fastest I want this to go), the PWM of the timer (which is set up for 50% duty cycle with no prescaling), is sitting at about 500KHz. 

So I ask, is there something going on that I'm missing here?

[Tesla DeLorean]

Posted on April 09, 2012 at 20:59

Isn't there a synchronizer circuit parked on the timers input pins?

What is the TIMCLK, and the SYSCLK in this system?

[shotaro]

Posted on April 09, 2012 at 22:06

Isn't there a synchronizer circuit parked on the timers input pins?

If this is something external, then no. I just have an arbitrary function generator hooked up to GND and the input pin. I'm having an external oscillator circuit being made elsewhere, but I figured I'd use an arb to see what I can do.What is the TIMCLK, and the SYSCLK in this system? TIMCLK needs to be either 1.536MHz or 15MHz with no prescaling. SYSCLK is going to be the HSI. On my earlier thread, I was switching to the HSE as the SYSCLK as the timer was running off of it. But the clock had to be stable otherwise the timing would be thrown off and my timing requirements for this project are pretty insane.

[Tesla DeLorean]

Posted on April 09, 2012 at 23:33

Well HSI is going to be pretty sloppy if you have especially tight timing requirements. Each chip is unique due to process variations, there might be some trimming, but there is no thermal characterization over temperature as far as I'm aware. An external TCXO might be a better choice.

TIMCLK is typically APB or APB * 2, so if you're using HSI probably 16 MHz, check your APB divider settings and clock tree diagram. The circuit I'm talking about is internal, probably the ''FILTER'' block in the manual, but relates to bring input signals into sync with the internal clock domains. This might impose some nyquist limits, I haven't really thought about it, but it's definitely there to protect from glitches, and enforce setup/hold constraints. From RM0038 TIM2 to TIM4 features ''Synchronization circuit to control the timer with external signals and to interconnect several timers.'' ''The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal.''

[shotaro]

Posted on April 10, 2012 at 01:29

Sorry, should explain my setup better.

I'm running a timer through an external clock (16.3.3 in RM0038 details this) directly, since waiting for HSE and switching to that takes too long. The problem is when I do this and I output the clock signal more or less directly (the ARR and CCR registers are 1), the signal is jittery and significantly delayed. I've tried both External Clock 1 (through TI2) and External Clock 2 (ETR) and I get the same thing. I don't think the external goes through the APB prescaler (figure 101 is the setup, supposedly). But what's bugging me is when I do it all from SysClock, the signal's clean.

[Tesla DeLorean]

Posted on April 10, 2012 at 01:54

Fact 1 : The internal timers, registers, and other peripherals attached to the peripheral bus are synchronously clocked by the APB at some level, regardless of what you feed in externally on the inputs.

Fact 2 : Input signals are fed through a resychronizer circuit, probably three flip-flops but chat with an FAE, these will induce a phase-shift between the input clock from the outside, and the edge that clocks the timebase. Now I would imagine if you were sampling a 15.5 MHz signal at 16 MHz, one could expect it to rotate backward at 500 KHz. The actual effect will depend on the input circuit, and the assorted frequencies. It's called aliasing, and it's an effect described by Nyquist. Depending on how the frequencies ''beat'' together there will also be significant jitter as one is ''synchronized'' against the other.

[shotaro]

Posted on April 10, 2012 at 03:04

So basically at this point, using the external clock to drive a timer at 15MHz is a bad idea.

Which I'm sort of confused since I thought doing this was basically like feeding the timer some output instead of say CK_INT. Unless that edge detector is doing sampling and needs to be in compliance with the Nyquist theorem.