Posted on October 19, 2010 at 21:21This seem relatively serviceable using Keil, and writes to the flash, although I don't have a USART3 serial port. I've fixed the PLL code as I've previously suggested. If you want to locate faulting instructions, step through the code, you don't have much of it. Also you will need to work on erasing.
#include ''stm32F10x.h''
#define CR_PG_Reset ((uint32_t)0x00001FFE)
void setsystemclock(void);
/* EEPROM start address in Flash */
#define EEPROM_START_ADDRESS ((uint32_t)0x08010000) /* EEPROM emulation start address:
after 64KByte of used Flash memory */
#define FLASH_KEY1 ((uint32_t)0x45670123)
#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
int main(void)
{
char byte_temp=0;
int Address=0;
setsystemclock(); //set system clock to 24Mhz
RCC->APB2ENR |= RCC_APB2RSTR_IOPCRST | RCC_APB2RSTR_AFIORST;//port C clock and alternative clock enable. page 79
RCC->APB1ENR |= RCC_APB1ENR_USART3EN ;
GPIOC->CRH=GPIO_CRH_MODE10 | GPIO_CRH_CNF10_1 | GPIO_CRH_CNF11_0 ;//PC11 in input floating mode for RX. PC10 Alternative Output TX.
AFIO->MAPR=AFIO_MAPR_USART3_REMAP_0 ;//port remap as uart //PC10 TX PC11 RX
USART3->CR1 =USART_CR1_RE | USART_CR1_TE; //Receiver enable, Transmitter enable, USART disable
USART3->BRR = 0x9C4;//9600 at 24Mhz
USART3->CR1 |= USART_CR1_UE; //Uart Enable;
//flash configuration
FLASH->KEYR = FLASH_KEY1;
FLASH->KEYR = FLASH_KEY2;
FLASH->CR |= FLASH_CR_PG; //flash programing
Address = EEPROM_START_ADDRESS + 2;
*(__IO uint16_t*)Address = '6';
/* Wait for last operation to be completed */
while((FLASH->SR&FLASH_SR_BSY) >0);
/* if the program operation is completed, disable the PG Bit */
FLASH->CR &= CR_PG_Reset;
while(1)
{
if (((USART3->SR) & USART_SR_RXNE)>0)
{
byte_temp += USART3->DR;
if (((USART3->SR) & USART_SR_TXE)>0)
USART3->DR = (*(__IO uint16_t*)Address);
}
}
}
void setsystemclock(void)
{
RCC->CR |= RCC_CR_HSEON;
// Wait until it's ready
while ((RCC->CR & RCC_CR_HSERDY) == 0)
;
// Select PREDIV1 as PLL source and sett PLL mul to 3 (set bit 0)
// for 8*3 = 24 MHz
RCC->CFGR |= RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL_0;
// Start PLL
RCC->CR |= RCC_CR_PLLON;
// Wait until it's ready
while ((RCC->CR & RCC_CR_PLLRDY) == 0)
;
// Select PLL as system clock
RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL;
// Wait until PLL is used as system clock source
while ((RCC->CFGR & RCC_CFGR_SWS) != 0x08)
;
// Here we can check if PLL is used, and maybe disable HSI
// Disable HSI
RCC->CR &= ~RCC_CR_HSION;
RCC->CFGR|=RCC_CFGR_MCO_2; //sys clock output
}
