Posted on October 29, 2015 at 23:55> Do you have some clocking requirement which prevents you to use the
24.576
MHz oscillator (or, better, half of that) as the main clock source?
Yeah I thought of that too, if I use a 12.288 MHz oscilator as main clock with m=8, I can use the I2SPLL to get the 98.304 MHz I2S clock (N=128, Q =2).
I've noticed that the SAI-blocks are a bit more flexible in their clock generation than I2S, with SAI it seems I can even get Fs = 192 KHz with MCLK = 128 x Fs (that's what my ADC & DAC need at that samplerate, for others they take 256 x Fs).
The main clock would then be 179,712 MHz with main PLL N=234, P=2.
But, for accurate 44.1 KHz and their sibling sample rates, I would need a 11.2896 MHz oscilator. I can enable them seperately with GPIO's, but then I'd need to switch over to the internal 16 Mhz HSI during the changing of oscillators. So:
-Disable SAI
-Disable PLLSAI
-Set clock mux to HSI
-Disable Main PLL
-Disable external oscillator 1 (12.288 MHz)
-Enable external oscillator 2 (11.2896 MHz)
-Setup Main PLL to almost 180 MHz
-Re-enable Main PLL
-Set clock mux to PLLCLK
-Re-enable PLLSAI with N=128, R =4
-Re-nable SAI
Does this seem at all feasible or in any way possible? When setting the clock mux to HSI in CubeMX, it says that HCLK must be at least 30 MHz. So why offer this possibility?
The reason I'm contemplating this complex setup is because I would really like to use the ADC and DAC I've planned, without any samplerate error.
Cheers,
Tim
