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Pin mapping USB and JTAG/TRACE

deanclaxton
Associate II
Posted on June 17, 2011 at 02:02

Hi everyone,

I've just ordered the STM3220G-EVAL, but while waiting for it to arrive, I'm looking at pin mapping for my application.

In particular I have a couple of questions in regard to USB FS, and JTAG/TRACE.

USB FS

======

If I use port PB14 (OTG_HS_DM) and port PB15 (OTG_HS_DP), must I use port PB13 for Vbus as per the datasheet? Looking at the alternate function mapping I cannot see any particular mention of having to use PB13 for a specific function. Can I use any GPIO port?

JTAG/TRACE

==========

Is there a bare minimum recommendation of port pins to reserve for JTAG/TRACE? 

For example, does the serial wire have the same capabilities as the full JTAG? If I can get away with serial wire pins only, then I can free up SPI1.

Also in regard to trace there seems to be many different configurations - is there a bare minimum recommended, or can I get away without trace at all?

I'm completely new to STM32 (and to ARM Cortex full stop) - the remapping exercise is pretty interesting. Looks like NXP do the same with their LPC1850, but I cant get Ethernet AND SDIO out on theirs!

4 REPLIES 4
Posted on June 17, 2011 at 12:47

or can I get away without trace at all?

The answer will depend greatly on your debugging skills. Trace is helpful in the ''how the heck did my code ever get here'' scenarios. A lot of us older guys can figure that out with telemetry, properly instrumented fault handlers, stack dumps and static analysis.

Trace on the cortex series parts is some what faked, it records flow data rather than internal state per-se, and then reconstructs/back-annotates that flow onto host side compiled objects and source files. As a consequence if you want to trace old code, from a device in the field, you'd better hope your source code management permits you regenerate a suitable debug context.
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deanclaxton
Associate II
Posted on June 17, 2011 at 13:05

Thanks Clive,

I'll err on the side of caution and reserve some or all of the TRACE pins given that I am completely new to this architecture.

Dean

Posted on June 17, 2011 at 13:32

The dev board schematics should be a good starting point, put the TRACE pins on the last to consume list.

The biggest problem is providing access to the pins, even if you end up using them for peripherals, give yourself access and the ability to remove/disable those peripherals, that'll give you a window to trace on a subset of the board's totally functionality.

Hey, at least you're thinking about this. I can't tell you the number of times I've asked people to expose signals (debug, programming, etc) to a pin header, only for them to bury them, unused, under a BGA part or something.

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alok472
Associate II
Posted on June 20, 2011 at 06:19

The schematics of the eval board can be re-used for making your own schm.

The User manual of the board is available here.

http://www.st.com/internet/evalboard/product/250374.jsp