How to get STM32F207 or STM32F217 lowest jitter 50MHz output

[pmoore]

Posted on June 22, 2011 at 00:03

I have three questions regarding clock configuration for the STM32F207 / STM32F217:

1. Is there any advantage to using any specific HSE frequency between 4MHz and 26MHz that is evenly divisible by 2, if the goal is to divide down to get the PLL input to 2MHz?  (This is assuming I am using a quality low-jitter clock source to begin with.) 2. To get the lowest jitter 50MHz clock for RMII PHY use that can be produced by the STM32F2xx, wouldn't best practice be to feed the 2MHz into the I2SPLL?  3. Is there any document that shows what the expected jitter performance of the PLL is and how it is expected to vary as the input frequency changes from 1MHz to 2MHz? #stm32

[js23]

Posted on June 22, 2011 at 11:30

There is some info in the F207/217 errata sheet about this issue. (PLL clock input is allowed to be higher than previously stated).

The solution I would prefer, if the PHY can do this (like the LAN8720A): Clock the PHY with the 25MHz crystal HSE output directly on MCO1 and let the PHY double the frequency and route this back to REF_CLK input. This way you avoid the PLL jitter completely. I must admit, I never tried this... try at your own risk...

[Tesla DeLorean]

Posted on June 22, 2011 at 18:50

Or if there is a way of using an external 50 MHz source, which is stable, supplying that to the Ethernet interface, and dividing that by 2 to feed the STM32F2's clocks.

[pmoore]

Posted on June 23, 2011 at 01:47 The F107 can handle 50MHz on the HSE input for this very reason (ST even shows you how to wire it in the datasheet for the F105/F107)...I don't understand why the later development F207 does not support the same feature. Yes, I could divide the 50MHz clock and feed the result to the HSE, but it seems wasteful and creates more noise.