Posted on September 14, 2017 at 16:22
Hi Jan,
- For the
HS mode
, the TRDT minimum value should be 0x9.
if ( USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH)
{
hpcd->Init.speed = USB_OTG_SPEED_HIGH;
hpcd->Init.ep0_mps = USB_OTG_HS_MAX_PACKET_SIZE ;
hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10U) & USB_OTG_GUSBCFG_TRDT);
}�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?- For the
FS mode
, the TRDT minimum value depends on the AHB frequency range, it should be configured as described in the table below:
else
{
hpcd->Init.speed = USB_OTG_SPEED_FULL;
hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ;
/* The USBTRD is configured according to the tables below, depending on AHB frequency
used by application. In the low AHB frequency range it is used to stretch enough the USB response
time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
latency to the Data FIFO */
/* Get hclk frequency value */
hclk = HAL_RCC_GetHCLKFreq();
if((hclk >= 14200000U)&&(hclk < 15000000U))
{
/* hclk Clock Range between 2-15 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xFU << 10U) & USB_OTG_GUSBCFG_TRDT);
}
else if((hclk >= 15000000U)&&(hclk < 16000000U))
{
/* hclk Clock Range between 15-16 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xEU << 10U) & USB_OTG_GUSBCFG_TRDT);
}
else if((hclk >= 16000000U)&&(hclk < 17200000U))
{
/* hclk Clock Range between 16-2 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xDU << 10U) & USB_OTG_GUSBCFG_TRDT);
}
else if((hclk >= 17200000U)&&(hclk < 18500000U))
{
/* hclk Clock Range between 2-5 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xCU << 10U) & USB_OTG_GUSBCFG_TRDT);
}
else if((hclk >= 18500000U)&&(hclk < 20000000U))
{
/* hclk Clock Range between 5-20 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xBU << 10U) & USB_OTG_GUSBCFG_TRDT);
}
else if((hclk >= 20000000U)&&(hclk < 21800000U))
{
/* hclk Clock Range between 20-8 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xAU << 10U) & USB_OTG_GUSBCFG_TRDT);
}
else if((hclk >= 21800000U)&&(hclk < 24000000U))
{
/* hclk Clock Range between 8-24 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0x9U << 10U) & USB_OTG_GUSBCFG_TRDT);
}
else if((hclk >= 24000000U)&&(hclk < 27700000U))
{
/* hclk Clock Range between 24-7 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0x8U << 10U) & USB_OTG_GUSBCFG_TRDT);
}
else if((hclk >= 27700000U)&&(hclk < 32000000U))
{
/* hclk Clock Range between 7-32 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0x7U << 10U) & USB_OTG_GUSBCFG_TRDT);
}
else /* if(hclk >= 32000000) */
{
/* hclk Clock Range between 32-180 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0x6U << 10U) & USB_OTG_GUSBCFG_TRDT);
}
}�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?I don’t see any mismatch between the information on the reference manual and the driver.
Please let me know if I misunderstood your request.
Many thanks and best regards,
Khouloud.
