Posted on January 22, 2018 at 10:57
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In RMs for 'F4/'F7/'F0 (I didn't check further), in SPIx_I2S prescaler register (SPIx_I2SPR) chapter, I2SDIV description, the following statement is given:
I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values.
However, I've experimented with I2SDIV [7:0] = 1 back then - described in
https://community.st.com/0D50X00009XkYmHSAV
,I can't access it due to broken forum software
, original attachment shown below (MCLK in first two cases shown discontinuous as I chose inadequate sampling rate on LA... blushing... ). Results show, that I2SDIV [7:0] = 1 works as expected (dividing input clock by 2) as long as ODD = 0.It is beneficial to have as low divider for I2S as possible, as it lowers requirement for input clock (thus consumption and EMI).
Can please ST review this description and, if there's no other catch, allow I2SDIV[7:0]=1 provided that ODD = 0?
Thanks,
Jan Waclawek
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