Posted on June 10, 2018 at 00:13Imen,
We are interested to know what do you expect exactly in these sections.
As in all sections, I expect precise and exhaustively complete information, helping the reader in understanding of how to use the given peripheral... I thought I am known for this by now... 🙂
Chapter 27.3.6 Data reception management deals with what happens when data arrive and are decoded as valid:
The valid data contained into the RX_BUF will be immediately transferred into SPDIFRX_DR if SPDIFRX_DR is empty.
But, how would the user know this happened? This process is signaled in some way to the user. And it is the SPDIFRX_SR.RXNE flag, which signals this event to the user. So, I expect, that this would be mentioned alongside the description how the data are moved around.
The same goes for SPDIFRX_SR.CSRNE in the subsequent chapter. So it also should say, after
When 8 channel status and 16 user data bits have been received, they are packed and stored into SPDIFRX_CSR register.
that this is indicated by setting SPDIFRX_SR.CSRNE.
Note, that I am more concerned by the user's perception and less by the internal working of the peripheral. This is, because the RM is (or should be) targeted at users (and I am one of those users), thus, it should be less of an internal description for those who developed the module or integrate it into the SoC at ST (as is obviously the state of that particular chapter now). This should be the primary focus of technical writer who writes chapters in RM. He or she should be able to read it from the perspective of a reader, who is technically skilled but has never used this particular peripheral; and the result should be so that a sequential reading a module's chapter the reader should yield a complete picture of the modules' working, without requiring the user to go forth and back between the registers subsection and the narrative, and guess the internal connections of the registers, flags, signals, and the modules' logic.
Jan
