SRAM with Hardware parity checking: What's that?

[flyer31]

Posted on July 23, 2013 at 15:03

In the summary for the STM32F050C4 device (and also for other STM32F0 devices, e. g. STM32F030), I find the statement:

''4 Kbytes of SRAM with HW parity checking'' This term also appears in the summary list at the beginning of the datasheets. But if I search for ''HW parity'' or ''hardware parity'' in the reference manual, I get hits only in the UART description. Anybody knows, what this ''HW parity checking'' means, how it works, and whether it is also available in higher devices like STM32F4?

[Tesla DeLorean]

Posted on July 23, 2013 at 15:22

It's presumably just like the old PC memory which used 9x 1-bit wide memories for each byte, and computed parity just like a UART, it would compute/write the parity bit on memory writes, and on reads it would regenerate the parity bit and compare with that in memory, and then generate an NMI on failure. These days server memory sticks support 36-bit wide memory for 32-bit data, and use the 4 extra bits for ECC, which depending on the type of failure can detect and correct.

http://my.safaribooksonline.com/book/hardware/upgrading-and-repairing/9780789736970/memory/ch06lev1sec23

http://en.wikipedia.org/wiki/RAM_parity

[waclawek.jan]

Posted on July 23, 2013 at 15:37

> Anybody knows, what this ''HW parity checking'' means, how it works,

RM0091, ch.2.3 JW

[Chris1]

Posted on July 23, 2013 at 15:47

SRAM hardware parity checking is not an included feature of the STM32F405 / STM32F407 devices, I don't know about the others.

[Amel NASRI]

Posted on July 24, 2013 at 10:59

whether it is also available in higher devices like STM32F4?

In STM32F4 no, but this feature is available in STM32F3 products. -Mayla-