Bit set/reset timing

[Nevyn]

Posted on May 18, 2014 at 09:52

I am doing some work which requires precise timing and I think the STM8S can do what I need.  In order to prove this I setup a simple program which toggles PD0 in a while loop.

I am using the IAR compiler and it compiles the following:

PD_ODR = 0;

PD_ODR = 1;

to:

clr PD_ODR

mov PD_ODR, ♯?b1

The clear instruction operates in 1 clock cycle but the mov takes 2 cycles.  I decided to try the inline assembler and changed the C statement to:

asm(''bres PD_ODR, &sharp0'');

asm(''bset PD_ODR, &sharp0'');

PM0044 states that these instructions should take 1 cycle each but they both appear to take 2 cycles.

Has anyone seen this?  I'm wondering if PM0044 is correct.Regards,Mark #timing-stm8s-instruction

[fggnrc2]

Posted on May 19, 2014 at 06:59

Hello Mark.

The STM8 core has got a pipelined execution unit, so instructions seem to execute faster. Your code shows that a pipelined unit can't speed all code. BRES and BSET take both two bus cycles to complete. These bus cycles can't be completed while the following instruction runs and this is the reason for your measurements. BR EtaPhi