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STM8L Sleep Speed

MuratUrsavas
Associate III
Posted on October 08, 2012 at 08:40

OK, title sounds really weird, but I'm really curious about the low pawer state switch speed of the STM8L micro.

I'm doing some tests about switching to LSE and back to HSI, waiting for stablization etc. It looks like the core is acting really slow, or I'm doing something really wrong. Let me share my findings with you, and then please share your ideas with me. Note: I'm switching ON and OFF a GPIO to measure the passed time via scope. Therefore it could be good to keep in mind the switching time. I'm trying to simulate low power entrance and exit therefore you'll see opposite commands in same blocks. Here is a block of code. It runs in 630 us.

CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_LSE);
CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_HSI);

I'm widening the test and cover switch command. Runs in 1,09 ms.

CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_LSE);
CLK_SYSCLKSourceSwitchCmd(ENABLE);
CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_HSI);
CLK_SYSCLKSourceSwitchCmd(ENABLE);

Adding stability check and runs in 1,49 ms

CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_LSE);
CLK_SYSCLKSourceSwitchCmd(ENABLE);
while
(CLK_GetSYSCLKSource() != CLK_SYSCLKSource_LSE);
CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_HSI);
CLK_SYSCLKSourceSwitchCmd(ENABLE);
while
(CLK_GetSYSCLKSource() != CLK_SYSCLKSource_HSI);

Adding HSI enable disable procedure, completes in 2,30 ms

CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_LSE);
CLK_SYSCLKSourceSwitchCmd(ENABLE);
while
(CLK_GetSYSCLKSource() != CLK_SYSCLKSource_LSE);
CLK_HSICmd(DISABLE);
CLK_HSICmd(ENABLE);
CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_HSI);
CLK_SYSCLKSourceSwitchCmd(ENABLE);
while
(CLK_GetSYSCLKSource() != CLK_SYSCLKSource_HSI);

Finally adding ULP Voltage Regulator enable disable procedure, finishes in 3,23 ms

CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_LSE);
CLK_SYSCLKSourceSwitchCmd(ENABLE);
while
(CLK_GetSYSCLKSource() != CLK_SYSCLKSource_LSE);
CLK_HSICmd(DISABLE);
PWR_UltraLowPowerCmd(ENABLE);
PWR_UltraLowPowerCmd(DISABLE);
CLK_HSICmd(ENABLE);
CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_HSI);
CLK_SYSCLKSourceSwitchCmd(ENABLE);
while
(CLK_GetSYSCLKSource() != CLK_SYSCLKSource_HSI);

These results are really disappointing. There is no code for Peripheral Clock Gating and GPIO Switching or Interrupt clearance before the halt operation. Even so, it still takes almost 5 ms. Is it really so or am I missing something serious... Please share your low power ideas with me, don't think they are not related, they might be. Thanks in advance. P.S: I need as loweest state as possible with RTC timer enabled. #stm8l-low-power-halt
1 REPLY 1
MuratUrsavas
Associate III
Posted on October 09, 2012 at 09:09

Let me answer my own question partially. 

If I stop the core without bothering to switch clock sources & ULP Voltage Regulator, it sleeps and wakes up very fast. Didn't measure the sleep speed since I wasn't sampling the clock output, I can give you an idea of the wake up speed. 

It reacts to an interrupt in just 2.704 us (including GPIO set time). It looked like fast to me but keep in mind I haven't measured the final power consumption result yet.