SPI Interbyte delay

[srdjan]

Posted on February 27, 2015 at 19:44

Hi all,

I'm doing some testing with STM32L151, and I'm trying to send a bulk of data over SPI.I'm using SPI in interrupt mode, my CPU is set to 32MHz, SPI is set to 16MHz.When I send a byte, I'm waiting for a SPI_I2S_IT_TXE interrupt so that I can move another byte into the DR register, but when I look at my scope following occurs:I can see that SPI clocked out 8 bits of data, but the TXE interrupt fires approximately 2 byte intervals later. As far as I know, it should fire as soon as 1 bit is clocked out on the SPI. 1 byte is clocked out in 500nS (which is correct for 16Mhz), but then next byte is delayed approximately 1ms or even more. I have this gap of 2 byte intervals between bytes on the SPI. (See attached image)To make things even stranger, when I decrease the SPI speed to 8MHz, or 4MHz, this mechanism starts to work more reliably. I can see that the TXE interrupt fires much sooner after the 1st clocked out bit, and bytes are sent immediately one after another.Almost seems like the CPU is not able to transfer data from the DR to shift register fast enough.Any ideas what might be wrong? #stm32-stm32l151 #spi

[Tesla DeLorean]

Posted on February 27, 2015 at 21:08

Almost seems like the CPU is not able to transfer data from the DR to shift register fast enough. Any ideas what might be wrong?

Or that interrupting at 2 MHz is insane? Use DMA to service any thing >32KHz

[Tesla DeLorean]

Posted on February 27, 2015 at 21:22

Quick reality check :

32 MHz CPU 8-bit SPI at 16 MHz, byte time 2 MHz (500 ns), 16 processor cycles. Entry/Exit overhead for an interrupt that does nothing 22 cycles. You would do better sitting in a tight loop checking TXE

[srdjan]

Posted on February 27, 2015 at 21:45

Ahhh .. I see..

Thanks for the reply (and the reality check) 🙂

[childresss]

Posted on February 28, 2015 at 07:07

to get max SPI speed, I use DMA. No inter-byte delays.

The typical SPI speeds yield too many interrupts per second to be practical.