Posted on September 15, 2017 at 12:27Hi,
I have to handle some precise delays...
The pipeline on STM32F4 is 3 cycles. GPIO are connected on the AHB bus.
What is the delay required between a write to a GPIO register (first step of the pipeline) and the effective rising edge of the physical pin ?
(assuming no wait states, no event/interrupt, and only the core is mastering AHB bus.
Thanks
