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stm32F746 + sdram problem

Franzi.Edo
Senior
Posted on December 01, 2015 at 16:24

Hi,

I have an stm32F746 configured to run @ 216-MHz. My primary memory is an sdram configured on the block 2 (address 0xD0000000).

My memory tests (running from the flash) are all OK (many different tests under different environmental conditions (lower voltage, temperature, etc)).

Now, as soon as I try to execute a small code downloaded into this sdram memory (I verified the code in the sdram), I have an immediate exception (Hard Fault).

I tried many usual actions such as the reduction of the cpu speed, increased the memory timing etc. No way, I can safely read/write in the memory but I cannot execute any code.

On my previous targets (stm32F429) I never had this behaviour. The address 0xD0000000 seems not to be under any cache control.

So, any ideas of why I cannot execute programs on the sdram?

Regards

Edo

5 REPLIES 5
Nesrine M_O
Lead II
Posted on December 01, 2015 at 17:16

Hi Edo,

“So, any ideas of why I cannot execute programs on the sdram?�

The SDRAM bank 2 starting from 0xD0000000 is a never execute area as it is mentioned in the Cortex®-M7 default mapping.

So you need to modify the region attribute by using The Cortex®-M7 MPU.

-Syrine-

Franzi.Edo
Senior
Posted on December 01, 2015 at 17:48

Hi Syrine,

Thank you for this information. Of course, you are right. However, and like for my previous M4 designs, I have swapped the bank using the following instruction. Now the memory is seen at the address 0x70000000.

SYSCFG->MEMRMP = 0x400;

With this instruction I still have some strange behaviours (even if the programs do not crache immediately). In this mode I have the impression that it is a cache issue.

I don't know if the M7 at the start-up it has the caches activated. If yes, how to disable them before using the sdram? Of course, I decrease the performances, but at least I can continue to work.

Edo

Nesrine M_O
Lead II
Posted on December 02, 2015 at 09:27

Hi Edo,

1-You are using a custom board or an ST board?

2-“I don't know if the M7 at the start-up it has the caches activated�

By default, the Cortex®-M7 system caches (instruction and data caches) are disabled.

3-I recommended you to have a look to the FMC_SDRAM_MemRemap project under the STM32Cube F7 package, the example guides you through the different configuration steps to use the IS42S32800G SDRAM memory (mounted on STM327x6G-EVAL revB evaluation board) as code execution memory.

STM32Cube_FW_F7_V1.2.0\Projects\STM32756G_EVAL\Examples\FMC\FMC_SDRAM_MemRemap

-Syrine-

Franzi.Edo
Senior
Posted on December 02, 2015 at 09:30

Hi Syrine,

Thank you. Your information helped me to progress.

For 1. No, I have my own design

For 2. OK

For 3. OK, I will check again.

But in the meantime some progress:

I changed the attributes of a portion of the sdram area and now I can execute program inside the sdram.

I slowly progress but still remain a problem and maybe you will have an advise about.

So, now I can execute code but I cannot use the same physical sdram for locating a stack (or other R/W data).

As soon as my sdram running code access a data my system hangs (no exceptions!!).

Here is my sdram mapping

0xD00000000 - 0xD01FFFFF Heap

0xD02000000 - 0xD05FFFFF Executable area

0xD06000000 - 0xD07FFFFF Some data (images)

In order to make executable the area 0xD02000000 - 0xD05FFFFF I modified the MPU in the following way

// New attributes for the SDRAM area (0xD0200000)

// Change the attribute only in the executable area

MPU->CTRL = 0x00000000; // Disable the MPU

MPU->RNR  = 0x00000000; // Region 0

MPU->RBAR = 0xD0200000 | (1<<4) | (0<<0); // Address, valid & region 0

MPU->RASR = (0<<28) // Instruction fetches enabled

  | (3<<24) // Full access

  | (1<<19) // TEX: 001 Memory attribute

  | (1<<18) // S:     1

  | (1<<17) // C:     1

  | (1<<16) // B:     1 Sharable, Normal,

   // Outer and inner write-back.

// Write and read allocate

  | (0<<8) // Sub-region is enabled

  | (22<<1) // 4-MB

  | (1<<0); // Region enable

MPU->CTRL = (1<<2) // Enable the usage of all the

// default map

  | (0<<1) // MPU disabled during faults

  | (1<<0); // MPU enabled

__asm__ volatile (

''dsb \n''

''isb \n''

);

What is the solution to make possible the usage of the sdram for execution code and simultaneously for storing data without troubles?

Regards

  Edo

js23
Associate III
Posted on May 09, 2016 at 13:05

Hi Edo,

that is exactly the problem I have at the moment. Could you (or somebody else) solve it in the meantime?

Thanks,

Johannes