STM32F100RB UART Interrupt Problem

[jstuempfl9109]

Posted on September 21, 2012 at 10:44

Hello,

I'm currently trying to implement a UART driver with interrupt handling for the STM32F100RB on my Discovery board.

Therefore, the function UART_Init() configures the UART1 and enables the interrupts TC and RXNE. Exactly at this point, the interrupt service routine is executed one time. When I'm debuggin the software, I see that the bit USART_SR_TC in the uart status register is set. But it is not cleared by reading the status register (as it is described in the datasheet of the controller). For test purposes, I'm writing a data byte to the uart data register. Then, the interrupt service routine is executed all the time. Do I have to reset another interrupt flag (maybe in the NVIC?)?

Does anybody have a working uart code with interrupt usage?

Here's my code (the uart irq is enabled in the NVIC register, of course).

void UART_Init(void)

{   /* enable clock for UART */   RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);

  USART1->BRR = (24000000 / 115200);

  USART1->CR1 = (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE | USART_CR1_TCIE | USART_CR1_RXNEIE);

  /* init ringbuffer */

  ringbuffer_init(&uart_tx_ringbuffer_s, uart_tx_data_ac, UART_TX_BUFFER_LENGTH);

  uart_status_ec = UART_STATE_IDLE;

  USART1->DR = 0xAA;

}

void USART1_IRQHandler(void)

{   if ((USART1->SR & USART_SR_TC) != 0x00)   {     /* Transmission clompete interrupt */     uart_status_ec = UART_STATE_IDLE;   } }   Thanks, tobiflea

[Tesla DeLorean]

Posted on September 21, 2012 at 16:23

You had better be prepared to disable TX interrupts if you don't have data to send. Failure to do so will result in repeated tail-chaining, and no foreground code execution.

Using TXE is recommended as this signals as the holding register is moved to the shift register. TC signals when all data is exhausted. There are examples in the firmware library releases. The TC bit is cleared by the following software sequence: 1. A read from the USART_SR register 2. A write to the USART_DR register Note: The TC bit can also be cleared by writing a ‘0 to it. This clearing sequence is recommended only for Multibuffer communication.