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Problems with interrupts for STM32f051

evert2
Associate II
Posted on November 26, 2012 at 15:32

Hello all,

I'am porting an stm32f103 application to an stm32f051

It is a bootloader which loads an application via RS485

However I ran into problems with clearing the usart buffer.

The uart interrupt is enabled for downloading my application in packets of 128 bytes.

However during the actual erase and program the internal flash section the interrupts are disabled to avoid interrupts during programming or erase.

The problem is arising when I enable the interrupts again. Despite clearing the usart buffer and clearing pending IRQ's, after enabling the interrupts again I immediatly got interrupts.

Since I thought everything was cleared, I did not expect any interrupt.

Did I forgot to clear something?

Here is a part of my code:

     NVIC_InitStructure.NVIC_IRQChannel = USART_IT_1;

     NVIC_InitStructure.NVIC_IRQChannelPriority = 0;

     NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE;

     NVIC_Init(&NVIC_InitStructure);

      /* calculate flash address from ID */

      prgm_address = (ACP_PAGE_SIZE * fragment_idx) + START_OF_APPLICATION;

      /* erase page when crossing flash page boundary */

     if (!(prgm_address % FLASH_PAGE_SIZE))

      {

             FLASH_ErasePage(prgm_address);

      }

      /* save ACP page in flash */

      for(i=0; i<ACP_PAGE_SIZE; i+=4)

      {

        /* lsb is first */

        prgm_word = rx_buf[i+5] | (rx_buf[i+6]<<8) | (rx_buf[i+7]<<16) | (rx_buf[i+8]<<24);

              FLASH_ProgramWord(prgm_address + (u32)i, prgm_word); /* program word */

         }

      tx_buf[2] = rx_buf[2]; /* return ms byte fragment index */

      tx_buf[3] = rx_buf[3]; /* return ls byte fragment index */

      t_msg_length = 4;

       /*

      clear EE flag if last fragment stored

      if ready the user must reset the board (power down, up).

      */

     if(fragment_idx == (NR_OF_ACP_PAGES - 1))

     {

          EE_WriteVariable(EEPROM_BOOT_CHAR, APPL_VALID);

        EE_WriteVariable(EEPROM_TABLE_ADDRESS, 0x00); /* this holds the EEPROM resetAllUserValues switch */

        setbit(comm_flags,PROGRAMMING);

      }

      /* Prevent delayed response, the programming code can take too long for the master! */

      NVIC_ClearPendingIRQ(USART_IT_1);

      /* test is also dummy read to reset all error flags */

     while (USART_GetFlagStatus(USART1, USART_FLAG_RXNE))

     {

          USART_ReceiveData(USART1); /* read buffer */

      }

      USART_ReceiveData(USART1); /* read buffer */

   

    /* Enable the USART Interrupt */

     NVIC_InitStructure.NVIC_IRQChannel = USART_IT_1;

     NVIC_InitStructure.NVIC_IRQChannelPriority = 0;

     NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;

     NVIC_Init(&NVIC_InitStructure);

After this Init my program stucks, and doen't run the code after this interrupt anymore.

So it looks like interrupts or data is handled which is send during the time that the interrupt was not available. This is not what I want, I want to handle next available interrupt/data which has a new packet with data for me.

Downloading the complete application only works when I do not use the FLASH_ErasePage() function before I do the programming part. Since the FLASH_ErasePage is consuming around 20-40ms, it seems like in the meanwhile the buffer is filled and not erased.

Does somebody has any idea what is going on? did I forget to reset anything?

Thanks in advance

Evert Huijben

#interrupt-flash
3 REPLIES 3
Posted on November 26, 2012 at 16:56

What is USART_IT_1 ?

And why wouldn't you use USART_ITConfig() ?

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evert2
Associate II
Posted on November 27, 2012 at 09:15

Hi,

The USART_IT_1 is the interrupt of USART1, in this case 0x1B

I don't know why USART_ITConfig()  is not used, probably this is for historical reasons, since this code is allready used for a while.

However using USART_ITConfig() is not helping me.

But ... In the meanwhile I've found that disabling and enabling the USART completely will help (USART_Cmd(USART_NR, DISABLE), USART_Cmd(USART_NR, ENABLE))

Maybe someone can tell me why this not needed for a STM32f103 and really needed for a STM32f051. It looks like timing issues play a role.

However I'am glad that I have found this issue after a few days of fault finding.

Evert Huijben

Nickname12657_O
Associate III
Posted on November 28, 2012 at 17:18

''Maybe someone can tell me why this not needed for a STM32f103 and really needed for a STM32f051''

F0 USART programming procedure and registers are modified compared to F1 ones. This may explain issues you faced. You can refer to

http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/APPLICATION_NOTE/DM00052530.pdf

 for more details.

Cheers,

STOne-32