Problem on SPI3 of STM32F4-Discovery

[xinjin]

Posted on March 13, 2013 at 14:54

I would like to use SPI3 on STM32F4-Discovery. And the configuration is referred to the demo provided in the library. But when I use SPI_Write to debug it, there is no clock signal tracked by oscilloscope. The configuration of SPI3 is attached. Please help to find the issues. Appreciate.

[Tesla DeLorean]

Posted on March 13, 2013 at 15:37

Helps if you provide the #define's you're using here.

PB3 potentially clashes with JTDO/SWO, also you need to be sure that the SPI transaction is complete before releasing the CS. Other potential clashes with the CS43L22

[xinjin]

Posted on March 13, 2013 at 16:14

Thanks clive for your reply. I add the define as follows:

/* Analog Front End SPI Interface pins  */

#define

sAFE_SPISPI3

#define

sAFE_SPI_CLKRCC_APB1Periph_SPI3

#define

sAFE_SPI_CLK_INITRCC_APB1PeriphClockCmd

#define

sAFE_SPI_SCK_PINGPIO_Pin_10

#define

sAFE_SPI_SCK_GPIO_PORTGPIOC

#define

sAFE_SPI_SCK_GPIO_CLKRCC_AHB1Periph_GPIOC

#define

sAFE_SPI_SCK_SOURCEGPIO_PinSource10

#define

sAFE_SPI_SCK_AFGPIO_AF_SPI3

#define

sAFE_SPI_MISO_PINGPIO_Pin_11

#define

sAFE_SPI_MISO_GPIO_PORTGPIOC

#define

sAFE_SPI_MISO_GPIO_CLKRCC_AHB1Periph_GPIOC

#define

sAFE_SPI_MISO_SOURCEGPIO_PinSource11

#define

sAFE_SPI_MISO_AFGPIO_AF_SPI3

#define

sAFE_SPI_MOSI_PINGPIO_Pin_12

#define

sAFE_SPI_MOSI_GPIO_PORTGPIOC

#define

sAFE_SPI_MOSI_GPIO_CLKRCC_AHB1Periph_GPIOC

#define

sAFE_SPI_MOSI_SOURCEGPIO_PinSource12

#define

sAFE_SPI_MOSI_AFGPIO_AF_SPI3

#define

sAFE_CS_PINGPIO_Pin_3

#define

sAFE_CS_GPIO_PORTGPIOB

#define

sAFE_CS_GPIO_CLKRCC_AHB1Periph_GPIOB    

#define

sAFE_PDB_PINGPIO_Pin_0

#define

sAFE_PDB_GPIO_PORTGPIOD

#define

sAFE_PDB_GPIO_CLKRCC_AHB1Periph_GPIOD

/* Exported macro ------------------------------------------------------------*/

/* Select sAFE: Chip Select pin low */

#define

sAFE_CS_LOW

()

GPIO_ResetBits

(

sAFE_CS_GPIO_PORT

,

sAFE_CS_PIN

)

/* Deselect sAFE: Chip Select pin high */

#define

sAFE_CS_HIGH

()

GPIO_SetBits

(

sAFE_CS_GPIO_PORT

,

sAFE_CS_PIN

)

   

/* Select sAFE: Power Down Control pin low */

#define

sAFE_PDB_LOW

()

GPIO_ResetBits

(

sAFE_PDB_GPIO_PORT

,

sAFE_PDB_PIN

)

/* Deselect sAFE: Power Down Control pin high */

#define

sAFE_PDB_HIGH

()

GPIO_SetBits

(

sAFE_PDB_GPIO_PORT

,

sAFE_PDB_PIN

)

/* Exported functions ------------------------------------------------------- */

/******************************************************************************/

/* Functions Prototypes                                                       */

/******************************************************************************/

void

sAFE_Init

(

void

);

/* Writes data to SPI. */

unsigned

char

SPI_Write

(

unsigned

char

*

pBuffer

,

                        

unsigned

char

NumByteToWrite

);

/* Reads data from SPI. */

unsigned

char

SPI_Read

(

unsigned

char

*

pBuffer

,

                       

unsigned

char

NumByteToWrite

);

#ifdef

__cplusplus

}

[xinjin]

Posted on March 14, 2013 at 12:29

I changed CS to PD7. Now I can track data sending on oscilloscope. I used SPI_Write in the attachment to send 32-bits data. SPI_Write is write to send a byte every time. But I can only track 30 clocks between the CS toggle. Could you help check the SPI_Write function in the attachment to help find the problems. Appreciate.

[Tesla DeLorean]

Posted on March 14, 2013 at 14:40

As observed earlier, your code controlling the CS does not pay attention to when the last bit shifts over the interface.

[xinjin]

Posted on March 15, 2013 at 06:23

Thanks, clive. I am not sure if

while

(

SPI_I2S_GetFlagStatus

(

sAFE_SPI

,

SPI_I2S_FLAG_TXE

)

==

RESET

);

represent the waiting for sending end.

[Tesla DeLorean]

Posted on March 15, 2013 at 11:34

In my recollection TXE signals immediately after the holding register transfers it's content to the outbound shift register, and the first bit starts shifting out. RXNE might be a better indication that the last bit was received. Attaching a scope/analyzer might be instructive.

[xinjin]

Posted on March 15, 2013 at 14:06

Thanks clive. The problem is solved. I used BSY flag to indicate the last data transimission end. However, I got another problem on the pin struction. The slave chip is powered by 5V, and MOSI is 3.3V power supplied. So I configed the I/O to OD with NOPULL, but the MOSI can't not get down to zero, the lower level is about 1V and high level is 3.3V. The strange thing is that for the SCK signal, the pin structure is the same and can work from zero to 5V. I am not sure if it is because the CS43L22 hold the MOSI pin. As you known, I configed PC12 as MOSI which is also connected to CS43L22.

[miroslav]

Posted on January 27, 2014 at 13:38

Hi,

I have exactly same problem with SPI3 and st-link debugger.I configure MCU to not use JTDO but in debug mode when I look at AFIO register there is written some other value for SWJ_CFG(always 0x50) and I want it to be 0x20.I already work with SPI1 and SPI2 and they work perfect in interrupt and non-interrupt mode.How you solved your problem?there is little code: tmp = AFIO->MAPR; tmp &= 0xF8FFFFFF; tmp |= AFIO_MAPR_SWJ_CFG_JTAGDISABLE; AFIO->MAPR = tmp;   DBGMCU->CR &= ~DBGMCU_CR_TRACE_IOEN;it works same as GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE); All the best,Miroslav