Minimal Pulse width for triggering an EXT-Interupt

[andywild2]

Posted on February 02, 2015 at 18:28

Hello to all,

I am using an STM32F2xx with 120Mhz. An external interupt is triggered with a rising edge of a GPIO-Pin. I looked in the datasheet, but I could not find information about the minimum pulse width at the GPIO-Pin in such  case. How does the edge detector in the STM32F2xx work? Does it detect the edge only if the signal is stable for a certain amount of clock cycles after the edge? Thanks for your help! Andy

[Tesla DeLorean]

Posted on February 02, 2015 at 19:33

Well the pin is feed into a pin synchronizer to get it into the AHB's clock domain, and then I'd expect it to enter a chain of flip-flops which could then determine a state change.

An ST FAE might be able to provide you with a specific diagram or illustration, and timing requirements (setup, hold).

[andywild2]

Posted on February 02, 2015 at 20:44

Hello Clive,

thanks for the quick answer! I was wrong: There is an entry in the datasheet (I/O AC charakteristics): tEXTIpw = 10ns But please who does the synchronizer work? In a  previous thread you said: ''The inputs do have a resynchronizer on them which has nyquist sampling properties'' Is it a real flip-flop or sampling device? Thanks a lot Andy

[Tesla DeLorean]

Posted on February 02, 2015 at 21:47

I'd expect it to be a chain of at least three flip-flops.

https://filebox.ece.vt.edu/~athanas/4514/ledadoc/html/pol_cdc.html

8-10ns seems like the width I'd half expected, perhaps with a latency of the order 24-30ns Nyquist works in the digital domain too, if you get the rates wrong you'll observed all kinds of aliasing and beat effects.