Is series resistor necessary in SDMMC CLK line for impedance matching?

[anonymous.8]

Posted on September 25, 2017 at 21:21

Hi, I am using the STM32746NG on the STM32746NG-DISCO discovery board. I am accessing the on-board SDMMC connector at double bus speed, i.e. 48 MHz. According to the schematic for the DISCO board there is no series resistor in between port C12 and the SDMMC microSD connector. Everything seems to work well, although admittedly only tested at room temperature. I have seen some schematics on-line that recommend a 47 Ohm series resistor in the clock line, especially when clocking it at double speed. I assume that is to get a better impedance match and help reduce line reflections. I see the distance on the DISCO board is quite long, about 7cm or 70mm.

My production board will have the microSD card connector coupled quite closely to the STM32746NG with the trace length being no more than about 6mm. In that case can I get away with no series resistor as I would think line reflections at that short length would be negligible?

This is a cost sensitive product and every elimination of unnecessary parts helps, especially since I don't use 47 Ohm resistors anywhere else.

Thanks.

[John F.]

Posted on September 26, 2017 at 09:30

I don't think you need worry about a 6mm track. This is from Analog Devices MT-097 TUTORIAL 'Dealing with High-Speed Logic' :

WHEN ARE TRANSMISSION LINE TECHNIQUES NEEDED?

Much has been written about terminating PCB traces in their characteristic impedance, to avoid signal reflections. Tutorial MT-094 presents the basic design equations for microstrip and stripline transmission lines. However, it may not be clear when transmission line techniques are appropriate.A good guideline to determine when the transmission line approach is necessary is as follows:Terminate the transmission line in its characteristic impedance when the one-way propagation delay of the PCB track is equal to or greater than one-half the applied signal rise/fall time (whichever edge is faster).For example, a 2 inch microstrip line over an Er = 4.0 dielectric would have a delay of ~270 ps. Using the above rule strictly, termination would be appropriate whenever the signal rise time is < ~500 ps.A more conservative rule is to use a 2 inch (PCB track length)/nanosecond (rise/fall time) rule. If the signal trace exceeds this trace-length/speed criterion, then termination should be used.For example, PCB tracks for high-speed logic with rise/fall time of 5 ns should be terminated in their characteristic impedance if the track length is equal to or greater than 10 inches (where measured length includes meanders).

The fastest switching time (Output high to low level fall time and output low to high level rise time) quoted in the STM32F745xx STM32F746xx DataSheet is 2.5ns although that's a maximum. Cherry Clough EMI guidance hints that manufacturers often don't know or care what the minimum switching times are and certainly ST don't provide a figure in the DataSheet. However, even if the fastest time is 250ps you should still be OK.

If you want to calculate it, you'll need to have more information from ST about output characteristics and consider your PCB dielectric and use of strip lines etc.

[waclawek.jan]

Posted on September 26, 2017 at 10:09

manufacturers often don't know or care what the minimum switching times are

or they just don't publicly provide a figure to avoid unnecessary complaints from those who don't understand all the consequences of parasitics and voltage/temperature dependencies.

You can estimate the minimum output impedance from the drive capability of the output transistors, I'd say their max being roughly 2x the given value. The good thing on STM32 is that you can slew limit by software, if only in a few steps. I don't know use the 'F7 but look also at the compensation cell if it has one, if you target the highest frequencies (pity ST doesn't provide the interesting details on that one).

JW