I think I discovered a bug in stm32469i_discovery_sdram.c

[Paul Bruner]

Posted on December 15, 2016 at 20:24

The Discovery STM32469I advertises that it comes with 16mb of ram.  However, the discovery firmware only enables 11 bits so it only sees 8mb.

You can change line 168 to this and it will fix it

    //sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_11;

    sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;

Its been a few years so not sure why no one has caught this one considering its one of the few, if not only, discovery devices that have more than 8mb of SDRAM.

You might also want to change SDRAM_DEVICE_SIZE in the header but I don't see it used in many places

#stm32469i #stm32469i-disco

[Tesla DeLorean]

Posted on December 15, 2016 at 21:10

It's been a few years so not sure why no one has caught this one considering it's one of the few, if not only, discovery devices that have more than 8mb of SDRAM.

Some of us aren't using the HAL/CubeMX, been using 16MB here. Honest truth is most people don't scratch under the surface of the supplied code, let alone pull a data sheet and fix or touch anything.

Honestly the SDRAM initialization code for the DISCO boards has always been a bit sketchy, the SPL code in system_stm32f4xx.c only ever handled the EVAL boards, and the DISCO used different chips, connectivity, and banks.

https://plus.google.com/115989800086056924077/posts/f1rFDiQ1fry

 

Not sure I've publicly posted my code for the STM32F469I-DISCO but it does exist.

[Tesla DeLorean]

Posted on December 15, 2016 at 21:41 The original post was too long to process during our migration. Please click on the provided URL to read the original post. https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006I6qm&d=%2Fa%2F0X0000000bwi%2FU.BHJU6QkcPrWcFSRiCC4.Lk7r1z.CyGjrdJDWb9OYo&asPdf=false

[Tesla DeLorean]

Posted on December 31, 2016 at 23:33

So spent some time to modify the system_stm32f4xx.c for the STM32F469I-DISCO SDRAM (CPU @180 MHz, SDRAM @90 MHz)

...
#ifdef DATA_IN_ExtSDRAM
/**
 * @brief Setup the external memory controller.
 * Called in startup_stm32f4xx.s before jump to main. sourcer32@gmail.com
 * This function configures the external SDRAM mounted on STM32469I-DISCO board
 * This SDRAM will be used as program data memory (including heap and stack).
 * @param None
 * @retval None
 */
void SystemInit_ExtMemCtl(void)
{
 register uint32_t tmpreg = 0, timeout = 0xFFFF;
 register uint32_t index;
 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
 clock */
 RCC->AHB1ENR |= 0x000001FC;
 /* Connect PCx pins to FMC Alternate function */
 GPIOC->AFR[0] = 0x0000000C;
 GPIOC->AFR[1] = 0x00000000;
 /* Configure PCx pins in Alternate function mode */
 GPIOC->MODER = 0x00000002;
 /* Configure PCx pins speed to 50 MHz */
 GPIOC->OSPEEDR = 0x00000002;
 /* Configure PCx pins Output type to push-pull */
 GPIOC->OTYPER = 0x00000000;
 /* No pull-up, pull-down for PCx pins */
 GPIOC->PUPDR = 0x00000000;
 /* Connect PDx pins to FMC Alternate function */
 GPIOD->AFR[0] = 0x000000CC;
 GPIOD->AFR[1] = 0xCC000CCC;
 /* Configure PDx pins in Alternate function mode */
 GPIOD->MODER = 0xA02A000A;
 /* Configure PDx pins speed to 50 MHz */
 GPIOD->OSPEEDR = 0xA02A000A;
 /* Configure PDx pins Output type to push-pull */
 GPIOD->OTYPER = 0x00000000;
 /* No pull-up, pull-down for PDx pins */
 GPIOD->PUPDR = 0x00000000;
 /* Connect PEx pins to FMC Alternate function */
 GPIOE->AFR[0] = 0xC00000CC;
 GPIOE->AFR[1] = 0xCCCCCCCC;
 /* Configure PEx pins in Alternate function mode */
 GPIOE->MODER = 0xAAAA800A;
 /* Configure PEx pins speed to 50 MHz */
 GPIOE->OSPEEDR = 0xAAAA800A;
 /* Configure PEx pins Output type to push-pull */
 GPIOE->OTYPER = 0x00000000;
 /* No pull-up, pull-down for PEx pins */
 GPIOE->PUPDR = 0x00000000;
 /* Connect PFx pins to FMC Alternate function */
 GPIOF->AFR[0] = 0x00CCCCCC;
 GPIOF->AFR[1] = 0xCCCCC000;
 /* Configure PFx pins in Alternate function mode */
 GPIOF->MODER = 0xAA800AAA;
 /* Configure PFx pins speed to 50 MHz */
 GPIOF->OSPEEDR = 0xAA800AAA;
 /* Configure PFx pins Output type to push-pull */
 GPIOF->OTYPER = 0x00000000;
 /* No pull-up, pull-down for PFx pins */
 GPIOF->PUPDR = 0x00000000;
 /* Connect PGx pins to FMC Alternate function */
 GPIOG->AFR[0] = 0x00CC00CC;
 GPIOG->AFR[1] = 0xC000000C;
 /* Configure PGx pins in Alternate function mode */
 GPIOG->MODER = 0x80020A0A;
 /* Configure PGx pins speed to 50 MHz */
 GPIOG->OSPEEDR = 0x80020A0A;
 /* Configure PGx pins Output type to push-pull */
 GPIOG->OTYPER = 0x00000000;
 /* No pull-up, pull-down for PGx pins */
 GPIOG->PUPDR = 0x00000000;
 /* Connect PHx pins to FMC Alternate function */
 GPIOH->AFR[0] = 0x0000CC00;
 GPIOH->AFR[1] = 0xCCCCCCCC;
 /* Configure PHx pins in Alternate function mode */
 GPIOH->MODER = 0xAAAA00A0;
 /* Configure PHx pins speed to 50 MHz */
 GPIOH->OSPEEDR = 0xAAAA00A0;
 /* Configure PHx pins Output type to push-pull */
 GPIOH->OTYPER = 0x00000000;
 /* No pull-up, pull-down for PHx pins */
 GPIOH->PUPDR = 0x00000000;
 /* Connect PIx pins to FMC Alternate function */
 GPIOI->AFR[0] = 0xCCCCCCCC;
 GPIOI->AFR[1] = 0x00000CC0;
 /* Configure PIx pins in Alternate function mode */
 GPIOI->MODER = 0x0028AAAA;
 /* Configure PIx pins speed to 50 MHz */
 GPIOI->OSPEEDR = 0x0028AAAA;
 /* Configure PIx pins Output type to push-pull */
 GPIOI->OTYPER = 0x00000000;
 /* No pull-up, pull-down for PIx pins */
 GPIOI->PUPDR = 0x00000000;
/*-- FMC Configuration ------------------------------------------------------*/
 /* Enable the FMC interface clock */
 RCC->AHB3ENR |= 0x00000001;
 /* Configure and enable SDRAM bank1 */
 FMC_Bank5_6->SDCR[0] = 0x000019E4;
 FMC_Bank5_6->SDTR[0] = 0x01115351;
 /* SDRAM initialization sequence */
 /* Clock enable command */
 FMC_Bank5_6->SDCMR = 0x00000011;
 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
 while((tmpreg != 0) & (timeout-- > 0))
 {
 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
 }
 /* Delay */
 for (index = 0; index<1000; index++);
 /* PALL command */
 FMC_Bank5_6->SDCMR = 0x00000012;
 timeout = 0xFFFF;
 while((tmpreg != 0) & (timeout-- > 0))
 {
 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
 }
 /* Auto refresh command */
 FMC_Bank5_6->SDCMR = 0x000000F3;
 timeout = 0xFFFF;
 while((tmpreg != 0) & (timeout-- > 0))
 {
 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
 }
 /* MRD register program */
 FMC_Bank5_6->SDCMR = 0x00046014;
 timeout = 0xFFFF;
 while((tmpreg != 0) & (timeout-- > 0))
 {
 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
 }
 /* Set refresh count */
 tmpreg = FMC_Bank5_6->SDRTR;
 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000056A<<1));
 /* Disable write protection */
 tmpreg = FMC_Bank5_6->SDCR[0];
 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
/*
 Bank1_SDRAM is configured as follow:
 FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2;
 FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 6;
 FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4;
 FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 6;
 FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2;
 FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;
 FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2;
 FMC_SDRAMInitStructure.FMC_Bank = SDRAM_BANK;
 FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
 FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_12b;
 FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = FMC_SDMemory_Width_32b;
 FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
 FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_3;
 FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;
 FMC_SDRAMInitStructure.FMC_SDClockPeriod = FMC_SDClock_Period_2;
 FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_enable;
 FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_0;
 FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;
*/
}
#endif /* DATA_IN_ExtSDRAM */
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[Imen.D]

Posted on January 02, 2017 at 14:26

Dear

warlockd

‌,

Thank you for posting your feedback.I will share your issue to our development team for checkingand working on this case.

Best Regards

-Imen-