ADC Hang on STM32L051C8T3

[Thomas Watson]

Posted on June 26, 2017 at 01:13

I am experiencing some issues with the ADC on my L0. I configure it with PCLK as the input clock in CKMODE, start it up, and take a sample. Everything works fine. I then decide to set the oversampling mode (which is in the same register as the CKMODE bits) after the ADC has started, but the CKMODE bits get cleared and the ADC does not sample (EOC never happens). This clearing happens no matter what value I write to the register, including 0, the previous value of the CKMODE bits, or the previous value of the entire register. It seems that though the datasheet says the oversample configuration can be changed as long as ADSTART=0 (which is true), any write to the register is unsafe. Am I doing something wrong?

Attached is my code.

[waclawek.jan]

Posted on June 29, 2017 at 01:16

By writing to the whole ADC_CFGR2 register you write to the CKMODE field, regardless of whether the value in it changes or not. When you do this while the ADC is enabled (ADC_CR.ADEN = 1) it appears that the ADC core loses clock altogether and it does not finish a started conversion, nor does it go to disable state when ADC_CR.ADDIS is set, anymore.

So, before writing to ADC_CFGR2, disable the ADC (through ADC_CR.ADDIS, follow the prescribed procedure); make the change, and then enable the ADC again.

It may be that the ADC registers can be accessed half-word-wise or byte-wise, but the RM fails to specify this.

ST: please specify allowed register accesses in the ADC chapter; and also the conditions under which the various ADC_CFGR2 fields can be accessed.

JW