Bug On CubeMX 4.20.1? STM32F407 Triple Mode and DMA

[Pablo Leibovich]

Posted on April 07, 2017 at 16:53

Hi all!

I want to you use all of the ADC of the STM32F407VG in triple regular simultaneous mode and to save a buffer of samples in RAM with DMA.

I configure everything with CubeMX and when I debug it, I cannot access memory positions after the buffering. Getting inside the drivers, I found that the DMA channel of the ADC is configured as this:

hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;

hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;

Searching in the reference manual, I learned that the Common data register in triple mode has 32 bits, so the data is saved on the LSB of the register, but the memory transfer must be done with 32 bits. Reconfiguring the buffer to be 32 bit long and DMA:

hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;

hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;

It works ok!

My question is, is this a bug of CubeMX for not notificate that half word DMA is not possible?

Thanks to all!

#adc #multimode-adc #cubemx-f4 #cubemx

[Imen.D]

Posted on April 07, 2017 at 17:01

Hi

Leibovich.Pablo

,

Thank you for your reported issue. I will check this case and report it internally if confirmed.

Imen

[Cyril FENARD]

Posted on May 22, 2018 at 13:24

Hi

Leibovich.Pablo

‌,

I had look to RM0090 Reference manual'STM32F405/415, STM32F407/417, STM32F427/437 and STM32F429/439 advanced Arm®-based 32-bit MCUs', and i saw that:

'In direct mode (DMDIS = 0 in the DMA_SxFCR register), the packing/unpacking of data is

not possible. In this case, it is not allowed to have different source and destination transfer data widths: both are equal and defined by the PSIZE bits in the DMA_SxCR MSIZE bits are don’t care).'

So whenever configuring DMA of the master ADC, i.e. ADC1, CubeMx tool keeps 'Data Width' the same for the selectable data size of the peripheral and the data size of the memory.

End-user is free to select the size of the destination memory according to his choice, that is the data alignment.

But keep in mind to have size large enough to support the number of bit of the ADCs samples in triple mode use-case.

Hopping it clarifies.

Regards.

Cyril.