Posted on April 24, 2017 at 18:18
Hi all,
I'm having hard times in configuring SPI communication with a M95128 eeprom; I'm using SPI1 on a STM32F103 mcu, with following connection scheme:
PA.04 -> ~S (CS)
PA.05 -> C (CLK)
PA.06 -> Q (MISO)
PA.07 -> D (MOSI)
and here follows my configuration code snippet:
/*
* enable APB2 peripheral clock for SPI1
*/
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_AFIO, ENABLE);
/*
* configure pins used for SPI1
* PA.04 = CS
* PA.05 = SCK
* PA.06 = MISO (Master In/Slave Out)
* PA.07 = MOSI (Master Out/Slave In)
*/
GPIO_InitStruct.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_5;
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.GPIO_Pin = GPIO_Pin_6;
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOA, &GPIO_InitStruct);
/*
* The MISO, MOSI and CLK pins are now connected to their AF
* so that the SPI1 can take over control of the pins
*/
GPIO_PinLockConfig(GPIOA, GPIO_Pin_5);
GPIO_PinLockConfig(GPIOA, GPIO_Pin_6);
GPIO_PinLockConfig(GPIOA, GPIO_Pin_7);
/*
* configure CS (PA.04) as output Open Drain
*/
GPIO_InitStruct.GPIO_Pin = GPIO_Pin_4;
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_Out_OD;
GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIOA->BSRR = GPIO_Pin_4; // set CS (PA.04) high
/*
* configure SPI1 in Mode 0
* CPOL = 0 --> clock is low when idle
* CPHA = 0 --> data is sampled at the first edge
*/
SPI_InitStruct.SPI_Direction = SPI_Direction_2Lines_FullDuplex; // set to full duplex mode, seperate MOSI and MISO lines
SPI_InitStruct.SPI_Mode = SPI_Mode_Master; // transmit in master mode, NSS pin has to be always high
SPI_InitStruct.SPI_DataSize = SPI_DataSize_8b; // one packet of data is 8 bits wide
SPI_InitStruct.SPI_CPOL = SPI_CPOL_Low; // clock is low when idle
SPI_InitStruct.SPI_CPHA = SPI_CPHA_1Edge; // data sampled at first edge
SPI_InitStruct.SPI_NSS = SPI_NSS_Soft; // set the NSS management to internal and pull internal NSS high
SPI_InitStruct.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_256; // SPI frequency is APB2 frequency / 16 (4.5MHz)
SPI_InitStruct.SPI_FirstBit = SPI_FirstBit_MSB; // data is transmitted MSB first
SPI_Init(SPI1, &SPI_InitStruct);
SPI_Cmd(SPI1, ENABLE); // enable SPI1
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When I try to send a read status register instruction to the eeprom, I can see that the CLK correctly sends 8 pulses while the MOSI line stays stuck at 1, as shown by attached picture, thus resulting in a 0xFF sent to the eeprom instead of 0x05 (which is the opcode for read status register).
Any hint?
TIA,
CArlo
