Resetable DMA for predefind amount of transfers

[con3]

Posted on February 10, 2018 at 20:49

Hey everyone,

I've got a small issue.

I've got a Dma that fills a buffer(Double buffer so 2 actually) with data at every rising clock edge. I only want this clock to trigger the DMA 192 times until a reset signal is received. Once the reset signal is received, the DMA should just carry on where it left off, so position 193 of the buffer.

This image tries to portray what Im trying to do. I have 192 cycles of data, followed by junk until the reset signal is received.So I want the Timer to trigger the dma for 192 rising edges, stop and wait for reset and then repeat.

Essentially this is what my timer configuration is like. An input capture which triggers the dma every rising edge and then a slave mode set for reset.

If I cant do this directly on the timer, is there a way that I could cascade two timers, where the timer would come in between the 2.5 MHZ signal and the timer that triggers the dma, pass through the clock signal and stop once 192 pulses have been received and restart on reset.Something like this:

I've tried a few implementations with cascaded timers and gated mode, but due to the gated mode not resetting the counter it doesn't seem to help. I've also found nothing on the forum but seen a few similar questions.

Thanks in advance for any help.

Not sure if I'm missing something obvious >.<

dma-transfer nucleo input-capture-mode stm32f7

[Tesla DeLorean · Accepted solution]

Posted on February 10, 2018 at 21:49

Perhaps TIM1/TIM8, one shot, with a repetition count? ADC triggering from CCx

[con3]

Posted on February 10, 2018 at 22:51

Hi Clive,

thank you for the response.

I'm a little lost but think I have an idea of what you mean.

My understanding: one pulse mode would produce a pulse with a user fixed length and a repetition counter would produce N amount of pulses.

I think your referring to the following :

And looking at the reference manual:

I'd need to set the pulse length to 1 so it starts on the rising edge and stops on the falling edge of the input signal. The delay to 0 as I want no delay between the input and output pulse (Also enable fastmode by setting OCxFE).

I can't find much on the repetition counter for this mode, but I'm assuming it would produce 192 pulses at the output for 192 pulses at the input and then stop. Once the reset signal is received this process would restart?

Thank you for all the help thus far!

[Tesla DeLorean]

Posted on February 11, 2018 at 01:00

Is DMA pulling data from GPIO or ADC?

Repetition mode has the count cycle N times (CNT=0..ARR,0..ARR, etc), there will be 1 Update event and N CCx events

[con3]

Posted on February 11, 2018 at 01:35

It's pulling from GPIO, so 192 rising edges from the 2.5 MHz signal should result in 192 samples read from GPIO to memory by the Dma and then nothing should be read till the reset signal arrives. Then it should repeat the 192 read.