Posted on June 28, 2017 at 03:19Dear all
Useing CAN1 of STM32F205, 32-bit Mask Mode filter, filter bank 0-13 work all right for now.
Then I am trying to configurate CAN2SB = 28d, for letting CAN1 use all 28 filter banks.
But it doesn't work, here is my part of code, would you please help me?
Thx inadvance
void can_Init(void)
{
UCHAR i;
RCC->APB1ENR |= RCC_APB1ENR_CAN1EN; // Enable clock for CAN
RCC->APB1RSTR |= RCC_APB1RSTR_CAN1RST; // Reset CAN module
RCC->APB1RSTR &= ~RCC_APB1RSTR_CAN1RST; // Deactivate reset
CAN1->MCR = CAN_MCR_ABOM | CAN_MCR_INRQ; // Automatic bus-off managment, init request
CAN1->IER = CAN_IER_FMPIE0 | CAN_IER_FMPIE1; // Active interrupts
CAN1->BTR = ( ((CAN_1tq) << 24) | ((CAN_4tq) << 20)
| ((CAN_3tq) << 16) | (((APB1_CLK/(CAN_TQS * CAN_BITRATE)) -1) & 0x3ff) ); // Set bit timing
CAN1->FMR |= CAN_FMR_FINIT; // Set filter init, do default filter setup
CAN1->FMR &= ~CAN_FMR_CAN2SB;
CAN1->FMR |= (CAN_FMR_CAN2SB & (0x1C << 8)); // all the filters to CAN1 can be used.
CAN1->FM1R = 0x00000000; // Set all filters in Identifier mask mode
CAN1->FS1R = 0x0fffffff; // Set all filters to 32 bit
CAN1->FFA1R = 0x0aaaaaaa; // Even filters to FIFO0, odd filters to FIFO1
CAN1->FA1R = 0x00000000; // Disable all receive filters
CAN1->FMR &= ~ CAN_FMR_FINIT; // Clear filter init
NVIC_SetPriority(CAN1_RX0_IRQn,CAN_PRIO);
NVIC_EnableIRQ(CAN1_RX0_IRQn); // Enable FIFO 0 interrupt
NVIC_SetPriority(CAN1_RX1_IRQn,CAN_PRIO);
NVIC_EnableIRQ(CAN1_RX1_IRQn); // Enable FIFO 1 interrupt
CAN1->MCR &= ~ CAN_MCR_INRQ; // End of initialization
GPIOB->BSRR = GPIO_BSRR_BR_6; // CAN_S low
for(i = 0;i < CAN_NROF_RXMSG;i++){
can_buf_wptr[i] = 0;
can_buf_rptr[i] = 0;
}
}
// Setup and enable receive filter with index msg_index
void can_SetupFilter(UCHAR msg_index, UCHAR idsize, ULONG canid, ULONG mask)
{
ULONG id_val, mask_val;
volatile ULONG * can_filter_ptr;
UCHAR filter_index;
if (msg_index < CAN_NROF_FILTERS){
can_filter_ptr = &CAN1->sFilterRegister[0].FR1; // Pointer to first register in filter bank
filter_index = msg_index * 2;
if (idsize == CAN_STD_ID){
id_val = (canid << 21);
mask_val = (mask << 21);
} else {
id_val = (canid << 3) | 0x04; // Id with IDE bit set
mask_val = (mask << 3) | 0x04;
}
CAN1->FA1R &= ~ (1 << msg_index); // Deactivate filter
can_filter_ptr[filter_index] = id_val; // Set id
can_filter_ptr[filter_index+1] = mask_val; // Set mask
CAN1->FA1R |= (1 << msg_index); // Activate filter
}
}
