Posted on February 17, 2018 at 02:53/******************************* Unlock and set clock sources **********************/
PWR->CR = (1<<8); //Disable Backup Domain write protection
RCC->BDCR |= RCC_BDCR_RTCEN; //RTC clock enabled
RCC->BDCR |= RCC_BDCR_RTCSEL; //RTC clock source is HSE (Crystal)
/*************************** RTC pre divider (HSE/0-31)******************************/
RCC->CFGR |= 0x001F0000; //HSE divider pre RTC, 8Mhz/0x001F0000 = 4031hz
/****************************** RTC register Unlock *********************************/
RTC->WPR = 0xCA; //First key to unlock write access to RTC registers
RTC->WPR = 0x53; //Second key to unlock write access to RTC registers
/*********************** RTC A and S divider settings *******************************/
RTC->ISR = (1<<7); //Enter init mode, calendar counter stopped
//RTC->PRER = 0x00030000; //Prediv A,7bit, bitpos 22 to 16,
//RTC->PRER |= 0x00001000; //Prediv S,15bit,bitpos 14 to 0
RTC->PRER = 0x00031000;
RTC->ISR = (0<<7); //Exit init mode, calendar counter are running with new PRER value
/******************* RTC divider A/S output mux *************************************/
RTC->TAFCR |= RTC_TAFCR_ALARMOUTTYPE; //GPIO pin out (Alarm) set to PP
//RTC->CR = (0<<19); //Clear bit19 to enable 512hz mode
RTC->CR = (1<<19); //Set bit19 enable 1hz mode
RTC->CR |= RTC_CR_COE; //Calibration signal on pin PC13 enabled
PWR->CR = (0<<8); //Enable Backup Domain write protection.
Trying to use the A and S divider signals as plain programmable ref clocks , seams to work but the init process produces strange register settings and assignments sort of, perhaps im setting up the RTC the wrong way or over seeing stuff?
Strange issues:
0: When i single step code above the register reads reports strange settings.
1: RTCEN and RTCSEL is always selected prior to actual register setting and single step do not highlight
the register set/clear position.
2: Cant change both PRER if both set atomic. Can only change both if one is atomic, but can change both with one single non atomic register write despite refmanual states two separate register writes.
3: Writing to RTC->CR Calib signal 512hz/1hz multiplexer to set either output kills output clk signal rather then just switch, but signal appears again when then writing RTC_CR_COE.
4: Calib clk signal appears on GPIO pin already when writing HSE divider clock ratio well before writing RTC_CR_COE.
5: Whatever new register values written seams to be replaced with default values whenever power is recycled.
