Understanding SDRAM Better?

[Terence D]

Posted on February 11, 2018 at 08:07

Hi, I'm interested in better understanding how SDRAM works with the on the STM32F4 Discovery development boards.  For example, I have an STM32F429-Discovery.  It has 64-Mbit SDRAM on the board.

I've closely examined the FMC_SDRAM example in the STM32 Cube, have it running on the board, I've analyzed all of the FMC register tweaking it does to initialize the SDRAM.  Additionally, I've read through the SDRAM sections of Chapter 37 (SDRAM controller) of RM0090 (the STM32F429/439 Reference Manual) in detail.

I think what I'm really lacking is a fundamental understanding of how SDRAM works - i.e. typical communication between the processor and the SDRAM, necessary initialization steps, timings, etc.

I'm wondering if anyone can suggest a resource for this?  The only thing I can find is this book at Amazon:

https://www.amazon.com/Memory-Controllers-Real-Time-Embedded-Systems/dp/144198206X

  ...which I'm not sure is the best fit and would prefer to find a free resource if possible.

Anyone?

#sdram #stm32f4 #fmc

[Bogdan Golab]

Posted on February 11, 2018 at 09:22

Maybe this document will be  helpful:

http://www.eewebinar.co.kr/webinar/attach/webinar_stm32_20170511.pdf

 

[Jan Waclawek]

Posted on February 11, 2018 at 09:31

Have a look at an SDRAM datasheet, IMO the ISSI ones ar easier reading.

JW

[Terence D]

Posted on February 11, 2018 at 18:45

Thanks for the suggestions guys, I'll follow up accordingly.  One other thing: I'd love to analyze the signals between the STM32F429 pins assigned to the FMC and the SDRAM.  However, with clock speeds of 133-200 MHz, this of course will not be possible with my logic analyzer that has a max sample rate of 50 MHz.

After googling around a bit, it seems I'm out of luck as far as trying to find a logic analyzer that can sample at this frequency with a $350-$400 budget

:(

  ...If anyone thinks otherwise, I'd be all ears.

[Tesla DeLorean]

Posted on February 11, 2018 at 18:01

Would agree that the data sheets are reasonably enlightening, and frankly and understanding of classic DRAM with row/column access would help significantly. Perhaps some computer architecture texts?

SDRAM brings the ability to more automatically serve up consecutive data from the array, the predictable nature of this allows for wide access and pipelining internally so some of the inherent slowness can be decimated. Latency is still relatively long, but throughput rapid.