Timer update DMA generation problem

[EvgenS Po]

Posted on April 07, 2018 at 16:30

Hello! I'm working with stm32f042 MCU. My task is to read GPIO 8-bit data (7-0 bits) periodically, the faster, the better. I use timer 3 to generate DMA request and DMA channel 4. The idea is the following one: timer periodically generates DMA request on update event, so GPIO->IDR is read. But it doesn't work. Timer doesn't generate DMA request, DMA counter doesn't change, no GPIO reading happens.

Init code

//DMA channel 4

[EvgenS Po]

Posted on April 07, 2018 at 16:36

Init code

//DMA channel 4

RCC->AHBENR |= RCC_AHBENR_DMAEN;

  DMA1_Channel4->CPAR = (uint32_t) (&(GPIOA->IDR)); DMA1_Channel4->CMAR = (uint32_t)(GpioData);  DMA1_Channel4->CNDTR = Size;  DMA1_Channel4->CCR = DMA_CCR_MINC | DMA_CCR_TEIE | DMA_CCR_TCIE;   DMA1_Channel4->CCR |= DMA_CCR_EN;  NVIC_EnableIRQ(DMA1_Channel4_5_IRQn);  NVIC_SetPriority(DMA1_Channel4_5_IRQn,0);

//Timer 3

RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;

  //TIM3->CR2 |= TIM_CR2_MMS_1; //tried that, no results  TIM3->DIER = TIM_DIER_UDE;

//TIM3->DIER |= TIM_DIER_UIE | TIM_DIER_TDE ; //tried that, no results

TIM3->PSC = 47999;  TIM3->ARR = 100;  TIM3->CR1 |= TIM_CR1_CEN;

What am I doing wrong?

[waclawek.jan · Accepted solution]

Posted on April 07, 2018 at 17:10

Incorrect DMA channel?

JW

[EvgenS Po]

Posted on April 07, 2018 at 23:04

Thank you very much, waclawek.jan! That was it. I thought the source was TIM3_TRIG corresponding DMA channel 4.

By the way, what maximum data frequency can be achieved by using scheme 'timer-DMA-GPIO->IDR'?

[EvgenS Po]

Posted on April 08, 2018 at 00:50

Thank you.

[waclawek.jan]

Posted on April 08, 2018 at 00:06

See AN2548 .

JW