Missing pulse detection in the STM32F407?

[chuck guzis]

Posted on August 27, 2017 at 08:52

I've got an application where pulses arrive every 28 usec or so--I'd like to use the stm32f4 timers to detect when at least 4 pulses are missing.   It's easy enough to do in discrete logic, but I'd like to avoid that.

The problem would seem to be very simple--just reset a counter with each incoming pulse; if the counter manages to count up to a threshold, fire off an interrupt.   But even with a bottle of aspirin, I can't seem to wrap my head around how this might be done using the timers in the STM32F407.

Does anyone have any ideas?

[waclawek.jan · Accepted solution]

Posted on August 28, 2017 at 10:46

You want to reset the timer when a pulse arrives, for this connect the pulses source to CH1 or CH2, set the respective channel to input capture (TIMx_CCMR1.CC1(2)S=0b01), set the slave controller input to this channel (TIMx_SMCR.TS = 0b101 or 0b110) and set the slave controller to Reset mode (TIMx_SMCR.SMS=0b100). Set TIMx_PSC/TIMx_ARR so that it overflows upon the missing pulse and enable the timer TIMx_CR1.CEN=1. Maybe you want to set it to one-pulse mode.

JW

[chuck guzis]

Posted on August 28, 2017 at 20:36

Thank you, JW.  After sleeping on the problem, I came to the same conclusion.  I'm already using TIM1 to control DMA with each pulse, so I'm going to try TIM2 in slave mode triggered off of TIM1  to see if it does the trick.   F4 timer documentation can be very confusing.

The app note

http://www.st.com/content/ccc/resource/technical/document/application_note/7a/88/df/e3/d3/36/40/29/DM00169730.pdf/files/DM00169730.pdf/jcr:content/translations/en.DM00169730.pdf

seems to say that this is the way to do things (Section 1.2.3), but it's specific to the F429 and the L476, so I've got my pencil sharpened and fingers crossed that it will work on the 407.

[chuck guzis]

Posted on September 14, 2017 at 19:15

As a followup, here's what worked...

TIM1 is set to do GPIO DMA triggering via capture mode; TIM2 is in slave reset mode from OC1 output trigger source on TIM1.  TIM2's  output-compare register set for the 'deadman' time and triggers an interrupt when it expires, which then disables TIM1 and TIM2.   I tried setting TIM2 to OPM, but for some reason (maybe incompatibility with reset mode), that didn't work.

Since the pulse train can begin at any given time, I poll the pulse input line until the first pulse of a train is detected, then TIM2 is enabled.

I was a bit puzzled why I was getting an extra byte of data on the second and subsequent string of pulses.   It then occurred to me to DeInit() TIM1 after the first pulse train to clear any incipient DMA requests.