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STM32F429 NVIC Register Question

Kang Sung Gu
Associate II
Posted on September 15, 2017 at 15:03

I want to know the NVIC Register

There is a description of GPIO and INTERRUPT in the Reference DataSheet, but there is no description of NVIC Register

Where can I find the details of the Register below?

typedef struct

{

  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */

        uint32_t RESERVED0[24U];

  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */

        uint32_t RSERVED1[24U];

  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */

        uint32_t RESERVED2[24U];

  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */

        uint32_t RESERVED3[24U];

  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */

        uint32_t RESERVED4[56U];

  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */

        uint32_t RESERVED5[644U];

  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */

}  NVIC_Type;
4 REPLIES 4
Posted on September 15, 2017 at 16:22

IP[x] where x is the interrupt number (0-239, as implemented)

and ISER[x / 32] & (1 << (x % 32)) for bit level

The Data Sheet contains the interrupt numbers as I recall, and the enumeration is also in one of the include files.

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Posted on September 15, 2017 at 15:24

Thank you so much

Posted on September 22, 2017 at 12:59

Thank you Clive One