Setting nss_soft in Master (SPI)

Muzahir Hussain · ‎2018-02-17

Posted on February 17, 2018 at 23:00

I want to set NSS pin to software mode in master using STM32F103RB. But I've few questions?

In reference manual, they say,

In NSS Software mode, set the SSM and SSI bits in the SPI_CR1 register. If the NSS pin is required in output mode, the SSOE bit only should be set.

Now,

Why do we need to set SSI bit with SSM?

What is the purpose of SSOE bit?

#spi #stm32f103rb

Bogdan Golab · ‎2018-02-17

Posted on February 17, 2018 at 23:17

Out of my experience: I used the STM32L152RE + CubeMX to generate the app skeleton and had SPI HW NSS disabled (hardware NSS handling).

To set/clear the NSS (software way) I simply used HAL GPIO function:

HAL_GPIO_WritePin(GPIOB, PinXX, GPIO_PIN_SET) / HAL_GPIO_WritePin(GPIOB, PinXX, GPIO_PIN_RESET)

Muzahir Hussain · ‎2018-02-18

Posted on February 18, 2018 at 18:40

Thanks for the reply.

I am not using any library however, therefore if you could answer my question and tell me the purpose of SSI and SSOE bit and which bit should I set along with SSM for software Nss, I'll be grateful.

Bogdan Golab · ‎2018-02-18

Posted on February 18, 2018 at 19:17

I wanted to say that I change NSS state manually using GPIO. You do not need any library - just change pin state at the register level (set pin as output, and change the output register value). This pin is connected to the SPI chip - CS (Chip Select pin). This allows you to select the device on the SPI bus.

Bogdan Golab · ‎2018-02-18

Posted on February 18, 2018 at 19:20

You may find this doc interesting:

http://www.st.com/content/ccc/resource/training/technical/product_training/group0/3e/ee/cd/b7/84/4b/45/ee/STM32F7_Peripheral_SPI/files/STM32F7_Peripheral_SPI.pdf/_jcr_content/translations/en.STM32F7_Peripheral_SPI.pdf

Bogdan Golab · ‎2018-02-18

Posted on February 18, 2018 at 19:25

Taken from the Reference Guide. My understanding is that I use Software NSS management where the CS is driven manually without using NSS controlled by the MASTER SPI.

Slave select (NSS) pin management

Hardware or software slave select management can be set using the SSM bit in the

SPI_CR1 register.

• Software NSS management (SSM = 1)

The slave select information is driven internally by the value of the SSI bit in the SPI_CR1 register. The external NSS pin remains free for other application uses.

• Hardware NSS management (SSM = 0)

Two configurations are possible depending on the NSS output configuration (SSOE bit in register SPI_CR2).

– NSS output enabled (SSM = 0, SSOE = 1)

This configuration is used only when the device operates in master mode. The NSS signal is driven low when the master starts the communication and is kept

low until the SPI is disabled.

– NSS output disabled (SSM = 0, SSOE = 0)

This configuration allows multimaster capability for devices operating in master mode. For devices set as slave, the NSS pin acts as a classical NSS input: the

slave is selected when NSS is low and deselected when NSS high.

Muzahir Hussain · ‎2018-02-19

Posted on February 19, 2018 at 11:38

I am really sorry, but I am still confused. You said,

You do not need any library - just change pin state at the register level (set pin as output, and change the output register value). This pin is connected to the SPI chip - CS (Chip Select pin). This allows you to select the device on the SPI bus.

And I completely get this. However in reference manual they say,

Bit 8 SSI: Internal slave select: This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the IO value of the NSS pin is ignored.

How can I manually change the NSS state using GPIO when the I/O value is ignored by SSI bit?

Bogdan Golab · ‎2018-02-19

Posted on February 19, 2018 at 12:31

I verified my project and I set the SSM to 1 and use the GPIO to change the pin state (pin marked as NSS connected to the CS of the sensor). This is what I do:

/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,

Communication speed, First bit and CRC calculation state */

hspi->Init.NSS & SPI_CR1_SSM) |

hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation);

/* Configure : NSS management */

hspi->Instance->CR2 =

(((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode);

However the information you are pointing out is not clear to me as well. Frankly speaking I set the bits above and simply played with GPIO bits because I failed with HW NSS.

I googled the forum and found some information related to STM32F4. MAybe this will help you understand the issue (currently I do not access to my home lab to experiment with this again):

https://community.st.com/thread/39153-spi-master-nss-always-low-in-stm32f4