In what order are registers pushed into the stack after the exception occurs?

[Muzahir Hussain]

Posted on November 21, 2017 at 19:24

In Cortex M3, what is the order in which the register are pushed into the stack?

Which of the following orders are correct (if any)?

First Order:

      PC

      PSRx

      R3

      R2

      R1

      R0

      R12

      Link Register

Second Order:

      PC

      PSRx

      R0

      R1

      R2

      R3

      R12

      Link Register

Please Guide? Thanks in advance?

#cortex-m3 #stm32f103rb #exception #arm

[waclawek.jan]

Posted on November 21, 2017 at 19:34

JW

[Tesla DeLorean]

Posted on November 21, 2017 at 20:03

Where

R0 = [SP + 0]

R1 = [SP + 4]

etc

[Tesla DeLorean]

Posted on November 21, 2017 at 20:12

void hard_fault_handler_c(unsigned int * hardfault_args, unsigned int r4, unsigned int r5, unsigned int r6)

{  printf ('\n[Hard Fault]\n'); // After Joseph Yiu

  printf ('r0 = %08X, r1 = %08X, r2 = %08X, r3 = %08X\n',

    hardfault_args[0], hardfault_args[1], hardfault_args[2], hardfault_args[3]);  printf ('r4 = %08X, r5 = %08X, r6 = %08X, sp = %08X\n',    r4, r5, r6, (unsigned int)&hardfault_args[8]);  printf ('r12= %08X, lr = %08X, pc = %08X, psr= %08X\n',    hardfault_args[4], hardfault_args[5], hardfault_args[6], hardfault_args[7]);

  printf ('bfar=%08X, cfsr=%08X, hfsr=%08X, dfsr=%08X, afsr=%08X\n',

    *((volatile unsigned int *)(0xE000ED38)),    *((volatile unsigned int *)(0xE000ED28)),    *((volatile unsigned int *)(0xE000ED2C)),    *((volatile unsigned int *)(0xE000ED30)),    *((volatile unsigned int *)(0xE000ED3C)) );

  while(1);

}

[Tesla DeLorean]

Posted on November 21, 2017 at 20:13

See how it indexes hardfault_args here, we pass in SP as parameter ♯ 1, ie R0