tim3 rises all interrupt flags even though it shouldn't

[martin salko]

Posted on October 31, 2017 at 11:46

Hello, I have timer 3 setup like this:

ARR = 8400

PSC = 99

CCR1 = 4200

CCR2-4 = 0xFFFF

CR1.CEN = 1

DIER.CC1IE = 1

DIER.UIE = 1

when i run my code after one interrupt all interrupt flags get set to 1, obviously this shouldn't happen, since except for ccr1 other counters are set to value too high to be reached.

and DMAR gets set to 1, but i don't use dma on this timer, also the SR register suddenly cannot be cleared even by jlink.

I'm looking for any suggestion on what is happening and how can i potentially fix it.

[martin salko]

Posted on October 31, 2017 at 12:49

I found out that the resetting of SR register is due to timer not stopping while debugging. (I.e. the timer updates it while the program is paused)

but this still doesn't explain why the other flags get set when they shouldn't, so the problem still persists.

[Tesla DeLorean]

Posted on October 31, 2017 at 14:02

They aren't technically 'interrupts' the SR reflects latched events, and you then gate those with enables to signal the NVIC. As I recall CCx assert at Update.

Not that ARR = N - 1