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State of GPIOs for STM32H7 MCUs

Brendan Oddo
Associate

‎2018-02-05 10:35 PM

Posted on February 06, 2018 at 07:35

Hi can someone please point me to the relevant datasheet that describes the state of the STM32H7 GPIO pins during the following conditions:

1) During power up

2) Just after reset (when the Power On Reset is released)

My understanding is this:

1)

During power up - 

High Impedance

2) After

Power On Reset is released - 

Analog Input

In application mode, of course the state of the GPIO will be set according to user configuration.    

Cant seem to find this information in the STM32H7 data sheets

Many thanks.

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2 REPLIES 2
waclawek.jan
Guru

‎2018-02-06 12:25 AM

Posted on February 06, 2018 at 09:25

I don't see a reason why would GPIOs have different mode during and after reset (assuming power-on reset, and except when entering bootloader or exiting from some of the low power modes). However, there *is* a discrepancy in the RM: while the narrative in 11.3.1 General-purpose I/O (GPIO) says:

During and just after reset, the alternate functions are not active and most of the I/O ports

are configured in input floating mode.

whereas - contrary to 'F7 - the GPIO chapter indicates that most of the pins go to Analog mode in reset:

0690X00000609csQAA.png

I know it's unlikely to happen, but I'd 1ove to heare ST's take on this.

JW

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Brendan Oddo
Associate

‎2018-02-06 07:46 PM

Posted on February 07, 2018 at 04:46

Thanks for the feedback JW.

From reading through the data sheets and in particular Section 11 from the RM0433 Reference Manual for the STM32H7 I have determined the following:

During and just after reset the GPIO's are in the following state:

Pins PA15, PA14, PA13, 

PB4 and PB3

 on Ports A and B are set to 

JTAG-DP (Debug Port)  

PA15 = JTDI (Input, internal pull-up enabled)

PA14 = JTCK-SWCLK (Input, internal pull-down enabled)

PA13 = JTMS-SWDIO (Input, internal pull-up enabled)

PB4 = NJTRST (Input, 

internal pull-up enabled

 )

PB3 = JTDO/TRACESWO (Output, n

o pull-up, pull-down

)

The contents of the control registers are set to 

the following configuration:

GPIO_MODER = Alternate function mode

GPIO_OTYPER = Output push-pull

 

GPIO_OSPEEDR = PA15, PA14 and PB4 = Low speed, PA13 and PB3 = Very high speed

GPIO_PUPDR = PA15, PA13 and PB4 = Pull-up, PA14 = Pull-down, PB3 = 

No pull-up, pull-down

  

GPIO_IDR = Not Applicable 

GPIO_ODR = Not Applicable

GPIO_BSRR = Not Applicable

 

GPIO_LCKR = Port configuration not locked

GPIO_AFRL = Alternate Function 0 selected 

GPIO_AFRH = 

Alternate Function 0 selected

The remaining pins on Ports A to K are set to 

Analog m

ode

defined by the following configuration:

GPIO_MODER = Analog mode

GPIO_OTYPER = Output push-pull

GPIO_OSPEEDR = Low speed

GPIO_PUPDR = No pull-up, pull-down

GPIO_IDR = Not Applicable 

GPIO_ODR = Not Applicable

GPIO_BSRR = Not Applicable

 

GPIO_LCKR = Port configuration not locked

GPIO_AFRL = Alternate Function 0 selected 

GPIO_AFRH = 

Alternate Function 0 selected (note Port K 8..15 not supported)

Pin NameFunction (after reset)I/O State (after reset)

PA15JTDIInput, internal pull-up enabled

PA14JTCK-SWCLKInput, internal pull-down enabled

PA13JTMS-SWDIOInput, internal pull-up enabled

PB4NJTRSTInput, internal pull-up enabled

PB3JTDO/TRACESWOOutput, no pull-up, pull-down

All othersAnalog modeInput, no pull-up, pull-down

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