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jtag connectivity to custom board based out of stm32f7

sanjeev majumdar
Associate III
Posted on February 15, 2018 at 20:30

Hello 

we have a customized having stm32f769bitb MCU. i am able to connect JTAG in hotplug mode but when im trying normal and other mode i m getting error as 'cant reset the core'. also i tried connect under reset im getting the same error. the custom board has schematic similar to stm32f769i eval board. can anybody suggest where could be the problem??

i am able to see the power supplies are also ok providing 3.3v as well as 5v.

thanks in advance.

#stm32f7-jtag-connectivty
1 ACCEPTED SOLUTION

Accepted Solutions
Posted on February 16, 2018 at 20:06

BOOT0 should be low for normal operation.

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8 REPLIES 8
Posted on February 16, 2018 at 09:50

Do you connect NRST to your debug header?

Is NRST driven (push-pull) by anything else in your system/design?

Supply to AVDD?

Voltage at VCAP pins?

Correct capacitance placed at VCAP, low ESR, close to device?

Similar, but not same, perhaps highlight the differences and illuminate us?

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sanjeev majumdar
Associate III
Posted on February 16, 2018 at 16:14

- yes NRST connected to debug header, no push pull

VCAP has low ESR and closed to device, correct capacitance as per the evaluation board schematics.

voltage at vcap couldnt measure. kindly suggest what else i can see.

Posted on February 16, 2018 at 17:45

For external debug pods make sure VTarget pin is powered if those pods have drivers/buffers.

What make/model of debug pod? Using ST-Link or J-Link utilities? OpenOCD?

Not really looking to debug custom designs through a key-hole.

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Posted on February 16, 2018 at 18:04

i am using st-link/v2 jtag B 2018 02 and stlink utility as well as keil uvision 5.

Posted on February 16, 2018 at 18:14

The authentic external ST-LINK do require power to VTarget, voltage should be reported by ST-LINK Utilities as I recall.

A lot of the fake/counterfeit ones frequently just connect directly without buffers.

Code on the micro which reconfigures the SWDIO/SWCLK pins, disables SWD/JTAG, or goes into low power modes can be difficult to connect too. Check if behaviour improves if you pull BOOT0 high.

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Posted on February 16, 2018 at 19:51

in Hot plug mode i am able to see the target voltage as 3.2V but in other mode stlink detection is fail its showing. BOOT0 pin is pulled up high already.

Posted on February 16, 2018 at 20:06

BOOT0 should be low for normal operation.

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Up vote any posts that you find helpful, it shows what's working..
Posted on February 16, 2018 at 21:24

thanks its working now as we have a problem with reset circuit and we removed it and provided external pull up to NRST pin of JTAG. Finally made BOOT0 low for normal operation. Now JTAG is getting connected in normal, connect under reset as well as hot plug mode. We have to think about the reset circuit which provides reset once system reset or hard reset comes.