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Order of DCMI frame event, and linked DMA transfer complete interrupt

Chris Rice
Associate III
Posted on July 06, 2018 at 17:43

Hello, we are writing a camera driver on our STM32F769, roughly following the sample code.  The DCMI peripheral is configured and streams data into its data register (DCMI_DR).  A DMA stream (DMA2, Stream 1) is used to transfer the memory from the data register to a reserved area in SDRAM.  To take a snapshot, the DMA stream is started with continuous mode off, and to take a stream the DMA stream is started with continuous mode on.

This all works fine, the expected data ends up in the destination programmed into my DMA memory address.   Two points of confusion though:

1) the DMA transfer complete interrupt seems to happen *before* the DCMI frame event interrupt.  This is counterintuitive... I would think the DCMI would do it's thing and then notify the DMA to do its thing.  Or is the DCMI smart enough to know the DMA is linked to it, and delays its interrupt until the DMA transfer is complete?

2) My DMA transfer seems to be happening half as fast as my DCMI frame events.  It doesn't seem likely that the DMA transfer is taking longer than 1/50 sec (my frame event rate), so I'm missing every other one, does it?  What else could this be, do you think?  

Generally speaking I'm finding the 'linkage' between the DCMI and the DMA to be a little black-box-ish, I don't know how they are coordinating their own behaviors and notifications behind the scenes. 

Some notes: 

* The DMA stream is not using double buffering

* I have the DMA stream acting as the 'flow controller', not the peripheral (i.e., DMA_S1CR->PFCTRL = 0).

Thanks for any insight or thoughts!

#dcmi-dma-camera #stm32f7-hal-dcmi #dma-dcmi #dcmi-dma #stm32f7-dma #stm32-interrupt
2 REPLIES 2
Posted on July 06, 2018 at 18:42

I think you'll find the DMA is a pretty dumb memory shoveling device, the interrupts there are going to depend on the DMA settings and buffer sizes, and have little relationship to autonomous devices stuffing the data in.

Watch for FIFO in the peripheral or DMA to cause time displacement of signals vs delivery of data vs completion.

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Posted on July 09, 2018 at 02:21

Thank you Clive, that's a helpful rule of thumb.

And I'll go learn more about the FIFO aspects of DMA, I actually don't have a crisp image of how those behave yet either.