Getting started question -- do I have to enable the STM32F7 cache?

[Chris Rice]

Posted on May 01, 2018 at 17:58

Hello, I'm moving from 8-bit programming to an STM32f769, and it's a bit overwhelming.  I've been combing through source code and the datasheets, trying to decide where to use the supplied code and where to write my own.  I feel like writing my own is generally better because I will be closer to the hardware and understand more.  But it's pretty deep/complex with this kind of CPU.

My question is, the first command in the sample applications provided start with CPU_CACHE_Enable, which call SCB_EnableICache and SCB_EnableDCache, which manipulate the SCB-->ICIALLU, SCB-->CCR, and other registers.

Please forgive my naivete, but I'm coming from CPUs that don't even allow you to manipulate the cache... what if I don't do this (enable the cache)?  Is this an optimization, or something that is necessary to do?  If necessary, why is it even in code, why isn't it the reset behavior?

Thank you.  I'm unable to find a description at the right level for me, so any answers will be very helpful and get me pointed in the right direction (beyond the specific answer, I'm sure).

Thanks.

#stm32f7 #cache

[Tesla DeLorean]

Posted on May 01, 2018 at 19:05

Without the cache you expose the inherent slowness of the memories. You don't need to enable caches.

Review the ARM TRM (Technical Reference Manual) and Joseph Yiu's books on the Cortex-Mx series to get up to speed.

[Chris Rice]

Posted on May 01, 2018 at 19:12

Thank you very much.

[T J]

Posted on May 02, 2018 at 02:46

found this list of books;

https://www.bookdepository.com/author/Joseph-Yiu

 

is there a newer book ?

for M4 ?  ( is 'H7 / 'F7 is M4 ?)

which text is more appropriate for the 'F7 / 'H7 series ?

[Tesla DeLorean]

Posted on May 02, 2018 at 03:43

The F7/H7 use the Cortex-M7, the Mx series in general would be a good starting point for someone who's missed the last 30 years of ARM 32-bit processors.

https://www.elsevier.com/books/the-definitive-guide-to-arm-cortex-m3-and-cortex-m4-processors/yiu/978-0-12-408082-9

 

These things are a lot more similar than they are different. Memory mapped peripherals and a uniform 4GB address space are things that are going to be the most immediate challenges.

With caching, coherency, pipelines, write-buffers, super-scaler, and multi-threaded it's going to be a deeper dive. I can dig up some foundational RISC texts and CPU architecture reference if needed.

[T J]

Posted on May 02, 2018 at 04:35

In particular,  the security arrangements inside the H7. 

RM0433 is 3,178 pages. (Can you imagine that in a hardback book ?)

is that the ARM TRM that you mentioned ?

It seems a little daunting, certainly a lot easier to do a seminar / you tube.

It would be interesting to implement complete security, and ask someone to crack into the code.

Considering a stand alone unit like a microwave oven or a Digital Scope.

There is no need to upgrade the firmware.

I am leaning toward Level 2 protection, I hope it is good enough.

(hoping to solder up a new H7 board this month.)

[john doe]

Posted on May 02, 2018 at 06:33

>Considering a stand alone unit like a microwave oven or a Digital Scope.

>There is no need to upgrade the firmware.

you've never owned a chinese hot air rework station